Datasheet

49
AT89C51ID2
4289C–8051–11/05
Figure 17. PCA Compare Mode and PCA Watchdog Timer
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (See Figure 18).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH CL
CCAP nH CCA Pn L
ECOMn
CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCA PPn
16 bit comparator
Match
CCON
0xD8
PCA I T
Enable
PCA counter/timer
RESET *
CIDL CPS1 CPS0 ECF
CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write t o
CCAPnH
CF CCF2 CCF1 C CF0
CR
CCF3CCF4
10