Datasheet

43
AT89C51ID2
4289C–8051–11/05
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by software.
Table 28. CCON Register
CCON - PCA Counter Control Register (D8h)
Reset Value = 00X0 0000b
Not bit addressable
The watchdog timer function is implemented in module 4 (See Figure 17).
The PCA interrupt system is shown in Figure 15.
76543210
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number
Bit
Mnemonic Description
7CF
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF
may be set by either hardware or software but can only be cleared by software.
6CR
PCA Counter Run control bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4
PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
3 CCF3
PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
2 CCF2
PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
1 CCF1
PCA Module 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
0 CCF0
PCA Module 0 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.