Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 44 (16.59x16.59) 8-Bit 60 MHz I/O number 34

Table Of Contents

Features
Description
Block Diagram
SFR Mapping
Pin Configurations
Oscillators
- Overview
- Registers
- Functional Block Diagram
- Operating Modes
  - Reset
  - Functional Modes
- Design Considerations
  - Oscillators Control
  - Prescaler Divider
- Timer 0: Clock Inputs
Enhanced Features
- X2 Feature
  - Description
Dual Data Pointer Register DPTR
Expanded RAM (XRAM)
- Registers
Reset
- Introduction
- Reset Input
- Reset Output
Power Monitor
- Description
Timer 2
- Auto-Reload Mode
- Programmable Clock- Output
- Registers
Programmable Counter Array PCA
- PCA Capture Mode
- 16-bit Software Timer/ Compare Mode
- High Speed Output Mode
- Pulse Width Modulator Mode
- PCA Watchdog Timer
Serial I/O Port
- Framing Error Detection
- Automatic Address Recognition
- Registers
- Baud Rate Selection for UART for Mode 1 and 3
  - Internal Baud Rate Generator (BRG)
- UART Registers
Interrupt System
- Registers
- Interrupt Sources and Vector Addresses
Power Management
- Introduction
- Idle Mode
  - Entering Idle Mode
  - Exiting Idle Mode
- Power-Down Mode
  - Entering Power-Down Mode
  - Exiting Power-Down Mode
- Registers
Keyboard Interface
- Interrupt
- Power Reduction Mode
- Registers
2-wire Interface (TWI)
- Description
- Notes
- Registers
Serial Port Interface (SPI)
- Features
- Signal Description
- Functional Description
Hardware Watchdog Timer
- Using the WDT
- WDT During Power Down and Idle
ONCE(TM) Mode (ON Chip Emulation)
Power-off Flag
EEPROM Data Memory
- Write Data
- Read Data
- Registers
Reduced EMI Mode
Flash Memory
- Features
- Flash Programming and Erasure
- Flash Registers and Memory Map
- Flash Memory Status
- Memory Organization
- Bootloader Architecture
- ISP Protocol Description
  - Physical Layer
  - Frame Description
- Functional Description
- Flow Description
- API Call Description
Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
Ordering Information
- Change Log for 4289A - 09/03 to 4289B - 12/03
- 4289B - 12/03 to 4289C - 11/05
Packaging Information
- PLCC44
- VQFP44
Table of Contents

AT89C51ID2

4289C–8051–11/05

Table 22. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

Reset Value = XXXX XXX0b

Not bit addressable

76543210

-------SPIX2

Bit

Number

Bit

Mnemonic Description

7-Reserved

6-Reserved

5-Reserved

4-Reserved

3-Reserved

2-Reserved

1-Reserved

0 SPIX2

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.