Datasheet

147
AT89C51ID2
4289C–8051–11/05
External Data Memory Write
Cycle
External Data Memory Read Cycle
Serial Port Timing - Shift
Register Mode
Table 104. Symbol Description
T
QVWH
T
LLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
QVWX
ADDRESS A8-A15 OR SFR P2
T
WHQX
T
WHLH
T
WLWH
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
LLAX
T
AVDV
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid