Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
145
AT89C51ID2
4289C–8051–11/05
External Program Memory
Read Cycle
External Data Memory
Characteristics Table 101. Symbol Description
T
PLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2
ADDRESS A8-A15ADDRESS A8-A15
12 T
CLCL
T
AVIV
T
LHLL
T
AVLL
T
LLIV
T
LLPL
T
PLPH
T
PXAV
T
PXIX
T
PXIZ
T
LLAX
Symbol Parameter
T
RLRH
RD Pulse Width
T
WLWH
WR Pulse Width
T
RLDV
RD to Valid Data In
T
RHDX
Data Hold After RD
T
RHDZ
Data Float After RD
T
LLDV
ALE to Valid Data In
T
AVDV
Address to Valid Data In
T
LLWL
ALE to WR or RD
T
AVWL
Address to WR or RD
T
QVWX
Data Valid to WR Transition
T
QVWH
Data Set-up to WR High
T
WHQX
Data Hold After WR
T
RLAZ
RD Low to Address Float
T
WHLH
RD or WR High to ALE high