Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
14
AT89C51ID2
4289C–8051–11/05
Oscillators
Overview Two oscillators are available (for AT8xC51IxD2 devices only, the others part number
provide only the main high frequency oscillator):
• OSCA used for high frequency: Up to 40 MHz
• OSCB used for low frequency: 32.768 kHz
Several operating modes are available and programmable by software:
• to switch OSCA to OSCB and vice-versa
• to stop OSCA or OSCB to reduce consumption
In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature has been implemented between the selected oscilla-
tor and the CPU.
Registers Table 16. CKSEL Register (for AT8xC51Ix2 only)
CKSEL - Clock Selection Register (85h)
Reset Value = 0000 000’HSB.OSC’b (see Hardware Security Byte (HSB))
Not bit addressable
76543210
-------CKS
Bit
Number
Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0CKS
CPU Oscillator Select Bit: (CKS)
Cleared, CPU and peripherals connected to OSCB
Set, CPU and peripherals connected to OSCA
Programmed by hardware after a Power-up regarding Hardware Security Byte
(HSB).HSB.OSC (Default setting, OSCA selected)