Datasheet
Table Of Contents
- Features
- Description
- Block Diagram
- SFR Mapping
- Pin Configurations
- Oscillators
- Enhanced Features
- Dual Data Pointer Register DPTR
- Expanded RAM (XRAM)
- Reset
- Power Monitor
- Timer 2
- Programmable Counter Array PCA
- Serial I/O Port
- Interrupt System
- Power Management
- Keyboard Interface
- 2-wire Interface (TWI)
- Serial Port Interface (SPI)
- Hardware Watchdog Timer
- ONCE(TM) Mode (ON Chip Emulation)
- Power-off Flag
- EEPROM Data Memory
- Reduced EMI Mode
- Flash Memory
- Electrical Characteristics
- Absolute Maximum Ratings
- DC Parameters
- AC Parameters
- Explanation of the AC Symbols
- External Program Memory Characteristics
- External Program Memory Read Cycle
- External Data Memory Characteristics
- External Data Memory Write Cycle
- External Data Memory Read Cycle
- Serial Port Timing - Shift Register Mode
- Shift Register Timing Waveforms
- External Clock Drive Waveforms
- AC Testing Input/Output Waveforms
- Float Waveforms
- Clock Waveforms
- Ordering Information
- Packaging Information
- Table of Contents
125
AT89C51ID2
4289C–8051–11/05
Boot Process
Figure 49. Bootloader Process
RESET
Hardware
condition?
BLJB!= 0
?
USER APPLICATION
Hardware
Software
FCON = 00h
FCON = F0h
FCON = 00h
?
Atmel BOOT LOADERUSER BOOT LOADER
yes = hardware boot
F800h
BLJB=1
BSB = 00h
?
SBV = FCh
?
PC=0000h
PC= [SBV]00h
conditions
BLJB=0
If BLJB=0 then ENBOOT bit (AUXR1) is set
else ENBOOT bit (AUXR1) is cleared
ENBOOT=1
ENBOOT=0
Yes (PSEN = 0, EA = 1, and ALE =1 or not connected)