Datasheet
85
AT89C51IC2
4301Dā8051ā02/08
Figure 36. Block Diagram
Address Register
Comparator
Timing &
Control
logic
Arbitration &
Sink Logic
Serial clock
generator
Shift Register
Control Register
Status Register
Status
Decoder
Input
Filter
Output
Stage
Input
Filter
Output
Stage
ACK
Status
Bits
8
8
7
8
Internal Bus
Timer 1
overflow
F
CLK PERIPH
/4
Interrupt
SDA
SCL
SSADR
SSCON
SSDAT
SSCS
PI2.1
PI2.0