Datasheet

AT89C51IC2

4301D–8051–02/08

Reset Value = 00X0 XXXXb

Not Bit addressable

Serial Peripheral DATa Register

(SPDAT)

The Serial Peripheral Data Register (Table 60) is a read/write buffer for the receive data

available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content

of the shift register.

Table 60. SPDAT Register

SPDAT - Serial Peripheral Data Register (0C5H)

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there

is no on-going exchange. However, special care should be taken when writing to them

while a transmission is on-going:

• Do not change SPR2, SPR1 and SPR0

• Do not change CPHA and CPOL

• Do not change MSTR

• Clearing SPEN would immediately disable the peripheral

• Writing to the SPDAT will cause an overflow.

1 -

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0 -

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Bit

Number

Bit

Mnemonic Description

7 6 5 4 3 2 1 0

R7 R6 R5 R4 R3 R2 R1 R0