Datasheet

65
AT89C51IC2
4301D–8051–02/08
Table 53. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
Reset Value = XXXX X000b
Not bit addressable
7 6 5 4 3 2 1 0
- - - - - SPIH TWIH KBDH
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 SPIH
SPI interrupt Priority High bit
SPIHSPILPriority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1 TWIH
TWI interrupt Priority High bit
TWIHTWILPriority Level
0 0 Lowest
0 1
1 0
1 1 Highest
0 KBDH
Keyboard interrupt Priority High bit
KB DHKBDLPriority Level
0 0 Lowest
0 1
1 0
1 1 Highest