Datasheet

5
AT89C51IC2
4301D–8051–02/08
Table 2. C51 Core SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stack Pointer
DPL 82h Data Pointer Low byte
DPH 83h Data Pointer High byte
Table 3. System Management SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
PCON 87h Power Control SMOD1 SMOD0 - - GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 - - M0 XRS1 XRS0
EXTRA
M
AO
AUXR1 A2h Auxiliary Register 1 - -
ENBOO
T
- GF3 0 - DPS
CKRL 97h Clock Reload Register - - - - - - - -
CKSEL 85h Clock Selection Register - - - - - - - CKS
OSCON 86h Oscillator Control Register - - - - - SCLKT0 OscBEn OscAEn
CKCKON0 8Fh Clock Control Register 0 TWIX2 WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1 AFh Clock Control Register 1 - - - - - - - SPIX2
Table 4. Interrupt SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1h Interrupt Enable Control 1 - - - - - ESPI ETWI KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1 B3h Interrupt Priority Control High 1 - - - - - SPIH TWIH KBDH
IPL1 B2h Interrupt Priority Control Low 1 - - - - - SPIL TWIL KBDL