Datasheet

AT89C51IC2

4301D–8051–02/08

Table 20. CKCON1 Register

CKCON1 - Clock Control Register (AFh)

Reset Value = XXXX XXX0b

Not bit addressable

7 6 5 4 3 2 1 0

- - - - - - - SPIX2

Bit

Number

Bit

Mnemonic Description

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 - Reserved

1 - Reserved

0 SPIX2

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,

this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.