Datasheet

20
AT89C51IC2
4301D–8051–02/08
– F
CLK CPU
and F
CLK PERIPH
, for CKRL<>0xFF
In X2 Mode:
In X1 Mode:
Timer 0: Clock Inputs Figure 4. Timer 0: Clock Inputs
Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.
SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode)
SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use
as periodic interrupt for time clock.
F
CPU
F=
CLK PE RIPH
F
OS C A
2 255 CKRL–( )×
----------------------------------------------
=
F
CPU
F=
CLK PE RIPH
F
OS C A
4 255 CKRL–( )×
----------------------------------------------
=
SCLKT0
1
0
FCLK PERIPH
:6
T0 pin
Sub Clock
C/T
1
0
OSCCON
TMOD
Gate
INT0
TR0
Timer 0
Control