Datasheet

19
AT89C51IC2
4301D–8051–02/08
Design Considerations
Oscillators Control • PwdOscA and PwdOscB signals are generated in the Clock generator and used to
control the hard blocks of oscillators A and B.
• PwdOscA =’1’ stops OscA
• PwdOscB =’1’ stops OscB
• The following tables summarize the Operating modes:
Prescaler Divider • A hardware RESET puts the prescaler divider in the following state:
– CKRL = FFh: F
CLK CPU
= F
CLK PERIPH
= F
OSCA
/2 (Standard C51 feature)
• CKS signal selects OSCA or OSCB: F
CLK OUT
= F
OSCA
or F
OSCB
• Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
– CKRL = 00h: minimum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSCA
/1020 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSCA
/510 (X2 Mode)
– CKRL = FFh: maximum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSCA
/2 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSCA
(X2 Mode)
0 1 X 1 1 IDLE MODE A
The CPU is off, OscA supplies the
peripherals, OscB can be disabled
(OscBEn = 0)
0 1 1 X 0 IDLE MODE B
The CPU is off, OscB supplies the
peripherals, OscA can be disabled
(OscAEn = 0)
1 X X 1 X
POWER DOWN
MODE
The CPU and peripherals are off,
OscA and OscB are stopped
Table 18. Overview (Continued)
PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment
PCON.1 OscAEn PwdOscA Comments
0 1 0 OscA running
1 X 1
OscA stopped by
Power-down mode
0 0 1
OscA stopped by
clearing OscAEn
PCON.1 OscBEn PwdOscB Comments
0 1 0 OscB running
1 X 1
OscB stopped by
Power-down mode
0 0 1
OscB stopped by
clearing OscBEn