Datasheet

17
AT89C51IC2
4301D–8051–02/08
Functional Block
Diagram
Figure 3. Functional Oscillator Block Diagram
Operating Modes
Reset A hardware RESET puts the Clock generator in the following state:
The selected oscillator depends on OSC bit in Hardware Security Byte (HSB) (see HSB
Table 84)
HSB.OSC = 1 (Oscillator A selected)
• OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped.
• CKS = 1: OscA is selected for CPU.
HSB.OSC = 0 (Oscillator B selected)
• OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped.
• CKS = 0: OscB is selected for CPU.
Functional Modes
Normal Modes • CPU and Peripherals clock depend on the software selection using CKCON0,
CKCON1 and CKRL registers
• CKS bit in CKSEL register selects either OscA or OscB
• CKRL register determines the frequency of the OscA clock.
XtalA2
XtalA1
XtalB1
XtalB2
OscBEn
OscB
OscA
CLK
CLK
Idle
CPU clock
OscAEn
CKS
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
1
0
:128
Sub
Clock
:2
X2
0
1
FOSCA
PERIPH
CPU
FOSCB
OSCCON
OSCCON
CKCON0
CKSEL
PwdOscA
PwdOscB
CKRL=0xFF?
1
0