Datasheet

AT89C51IC2

4301D–8051–02/08

Table 15. OSCCON Register

OSCCON- Oscillator Control Register (86h)

Reset Value = XXXX X0’HSB.OSC

’’HSB.OSC’b (see Hardware Security Byte (HSB)

Table 84)

Not bit addressable

Table 16. CKRL Register

CKRL - Clock Reload Register

Reset Value = 1111 1111b

Not bit addressable

7 6 5 4 3 2 1 0

- - - - - SCLKT0 OscBEn OscAEn

Bit

Number

Bit

Mnemonic Description

7 - Reserved

6 - Reserved

5 - Reserved

4 - Reserved

3 - Reserved

2 SCLKT0

Sub Clock Timer0

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

Cleared by hardware after a Power Up

1 OscBEn

OscB enable bit

Set by software to run OscB

Cleared by software to stop OscB

Programmed by hardware after a Power-up regarding HSB.OSC (Default

cleared, OSCB stopped)

0 OscAEn

OscA enable bit

Set by software to run OscA

Cleared by software to stop OscA

Programmed by hardware after a Power-up regarding HSB.OSC(Default Set,

OSCA runs)

7 6 5 4 3 2 1 0

- - - - - - - -

Bit

Number Mnemonic Description

7:0 CKRL

Clock Reload Register:

Prescaler value