Datasheet

137
AT89C51IC2
4301D–8051–02/08
External Data Memory Read Cycle
Serial Port Timing - Shift
Register Mode
Table 99. Symbol Description
Table 100. AC Parameters for a Fix Clock
Table 101. AC Parameters for a Variable Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
LLAX
T
AVDV
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid
Symbol
-M -L
UnitsMin Max Min Max
T
XLXL
300 300 ns
T
QVHX
200 200 ns
T
XHQX
30 30 ns
T
XHDX
0 0 ns
T
XHDV
117 117 ns
Symbol Type
Standard
Clock X2 Clock
X Parameter for -
M Range
X Parameter for -L
Range Units
T
XLXL
Min 12 T 6 T ns
T
QVHX
Min 10 T - x 5 T - x 50 50 ns
T
XHQX
Min 2 T - x T - x 20 20 ns
T
XHDX
Min x x 0 0 ns
T
XHDV
Max 10 T - x 5 T- x 133 133 ns