Datasheet

111
AT89C51IC2
4301D–8051–02/08
Table 88. Program Lock Bits of the SSB
Note: U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: don’t care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Flash Memory Status AT89C51IC2 parts are delivered in standard with the ISP boot in the Flash memory.
After ISP or parallel programming, the possible contents of the Flash memory are sum-
marized on Figure 42.
Figure 42. Flash Memory Possible Contents
Memory Organization In the AT89C51IC2, the lowest 32K of the 64 KB program memory address space is
filled by internal Flash.
When the EA pin is high, the processor fetches instructions from internal program Flash.
Bus expansion for accessing program memory from 32K upward automatic since exter-
nal instruction fetches occur automatically when the program counter exceeds 7FFFh
(32K). If the EA pin is tied low, all program memory fetches are from external memory.
Program Lock Bits
Protection Description
Security
level LB0 LB1
1 U U No program lock features enabled.
2 P U ISP programming of the Flash is disabled.
3 X P Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default After ISP
After Parallel
Programming
After Parallel
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP
Dedicated
ISP
7FFFh
Application
Virgin
or
Application