Datasheet

35
AT89C51IC2
4301D–8051–02/08
Programmable
Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
• Peripheral clock frequency (F
CLK PERIPH
) ÷ 6
• Peripheral clock frequency (F
CLK PERIPH
) ÷ 2
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• rising and/or falling edge capture
• software timer
• high-speed output
• pulse width modulator
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog
Timer", page 46).
When the compare/capture modules are programmed in the capture mode, software
timer, or high speed output mode, an interrupt can be generated when the module exe-
cutes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
The PCA timer is a common time base for all five modules (See Figure 11). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 26) and can be programmed to run at:
• 1/6 the
peripheral clock frequency (F
CLK PERIPH
)
• 1/2 the peripheral clock frequency (F
CLK PERIPH
)
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
PCA component External I/O Pin
16-bit Counter P1.2 / ECI
16-bit Module 0 P1.3 / CEX0
16-bit Module 1 P1.4 / CEX1
16-bit Module 2 P1.5 / CEX2
16-bit Module 3 P1.6 / CEX3