Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • • • – 8051 Pin and Instruction Compatible – Four 8-bit I/O ports + 2 I/O 2-wire Interface (TWI) Pins – Three 16-bit Timer/Counters – 256 bytes Scratch Pad RAM – 10 Interrupt Sources with 4 Priority Levels – Dual Data Pointer Variable Length MOVX for Slow RAM/Peripherals ISP (In-System-Programming) Using Standard Vcc Power Supply Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Loader High-speed Architecture – I
Description AT89C51IC2 is a high performance Flash version of the 80C51 8-bit microcontrollers. It contains a 32K bytes Flash memory block for program and data. The 32K bytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin.
AT89C51IC2 Block Diagram XTAL1 EUART + BRG PSEN SCL (1) SDA T2 (1) Flash RAM 256 x8 C51 CORE ALE/PROG T2EX (1) (1) (2) (2) XTAL2 PCA ECI Vss Vcc TxD RxD Figure 1.
SFR Mapping 4 The Special Function Registers (SFRs) of the AT89C51IC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) • Power and clock control registers: PCON • Hardware Watchdog
AT89C51IC2 Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low byte DPH 83h Data Pointer High byte 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - - GF1 GF0 PD IDL XRS1 XRS0 EXTRA M AO Table 3.
Table 5. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Table 6.
AT89C51IC2 Table 7.
Table 10. Two-Wire Interface Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SSCON 93h Synchronous Serial control SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 SSCS 94h Synchronous Serial Status SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 SSDAT 95h Synchronous Serial Data SSD7 SSD6 SSD5 SSD4 SSD3 SSD2 SSD1 SSD0 SSADR 96h Synchronous Serial Address SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSGC 7 6 5 4 3 2 1 0 Table 11.
AT89C51IC2 Table below shows all SFRs with their address and their reset value. Table 12.
Pin Configurations P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VCC XTALB2 P1.0/T2/XTALB1 P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 P1.4/CEX1 Figure 2. Pin Configurations 6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO 39 38 P0.4/AD4 P1.6/CEX3/SCK 7 8 P1.7/CEx4/MOSI 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 11 12 13 35 34 33 EA 14 15 32 31 PSEN 16 30 P2.6/A14 17 29 P2.5/A13 PI2.1/SDA P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 PLCC44 P0.5/AD5 PI2.0/SCL ALE/PROG P2.7/A15 P0.3/AD3 P2.
AT89C51IC2 Table 13. Pin Description for 40/44 Pin Packages Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function VSS 22 16 I Ground: 0V reference VCC 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0 - P0.7 43 - 36 37 - 30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs.
Table 13. Pin Description for 40/44 Pin Packages (Continued) Pin Number Type Mnemonic PLCC44 VQFP44 1.4 9 3 Name and Function I/O P1.7: Input/Output: I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller.
AT89C51IC2 Table 13. Pin Description for 40/44 Pin Packages (Continued) Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function SDA is the bidirectional 2-wire data line Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset.
Oscillators Overview Two oscillators are available for CPU: • OSCA used for high frequency: Up to 48 MHz @5V +/- 10% • OSCB used for low frequency: 32.768 kHz Several operating modes are available and programmable by software: • to switch OSCA to OSCB and vice-versa • to stop OSCA or OSCB to reduce consumption In order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature has been implemented between the selected oscillator and the CPU.
AT89C51IC2 Table 15.
Table 17. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 POF Power-Off Flag Cleared to recognize next reset type.
AT89C51IC2 Functional Block Diagram Figure 3.
Idle Modes Power Down Modes • It is always possible to switch dynamically by software from OscA to OscB, and vice versa by changing CKS bit. • IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL) • IDLE modes A and B depend on previous software sequence, prior to writing into PCON.
AT89C51IC2 Table 18. Overview (Continued) PCON.1 PCON.
– FCLK CPU and FCLK PERIPH, for CKRL<>0xFF In X2 Mode: F OSCA F CPU = F CLKPERIPH = --------------------------------------------- 2 × ( 255 – CKRL ) In X1 Mode: F OSCA F CPU = F CLKPERIPH = --------------------------------------------- 4 × ( 255 – CKRL ) Timer 0: Clock Inputs Figure 4. Timer 0: Clock Inputs FCLK PERIPH T0 pin Sub Clock :6 0 0 Timer 0 1 Control 1 C/T TMOD SCLKT0 OSCCON Gate INT0 TR0 Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock.
AT89C51IC2 Enhanced Features X2 Feature and OSCA Clock Generation In comparison to the original 80C52, the AT89C51IC2 implements some new features, which are: • The X2 option • The Dual Data Pointer • The extended RAM • The Programmable Counter Array (PCA) • The Hardware Watchdog • The SPI interface • The 2-wire interface • The 4 level interrupt priority system • The power-off flag • The Power On Reset • The ONCE mode • The ALE disabling • Some enhanced features are also located i
Figure 6. Mode Switching Waveforms XTALA1 XTALA1:2 X2 bit FOSCA CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON0 register (see Table 19) allow to switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is setting according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is actived. Setting the X2 bit activates the X2 feature (X2 mode).
AT89C51IC2 Table 19. CKCON0 Register CKCON0 - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Bit Number Mnemonic 7 I2CX2 Description 2-wire clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
Table 20. CKCON1 Register CKCON1 - Clock Control Register (AFh) 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Bit Number Mnemonic 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved 0 SPIX2 Description SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
AT89C51IC2 Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 21) that allows the program code to switch between them (Refer to Figure 7). Figure 7.
ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data poi
AT89C51IC2 Expanded RAM (XRAM) The AT89C51IC2 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51IC2 devices have expanded RAM in external data space; maximum size and location are described in Table 22. Table 22. Expanded RAM Address XRAM size Start End 1024 00h 3FFh AT89C51IC2 The AT89C51IC2 has internal data memory that is mapped into four separate segments. The four segments are: 1.
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory.
AT89C51IC2 Table 23. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - M0 - XRS1 XRS0 EXTRAM AO Bit Number Bit Mnemonic Description 7 - 6 - Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Pulse length 5 M0 Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default).
Timer 2 The Timer 2 in the AT89C51IC2 is the standard C52 the Timer 2. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is controlled by T2CON (Table 24) and T2MOD (Table 25) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
AT89C51IC2 Figure 9. Auto-Reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6 0 1 T2 C/T2 TR2 T2CON T2CON T2EX: (DOWN COUNTING RELOAD VALUE) if DCEN=1, 1=UP FFh FFh if DCEN=1, 0=DOWN (8-bit) (8-bit) if DCEN = 0, up counting TOGGLE T2CON EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CON RCAP2L (8-bit) TIMER 2 INTERRUPT RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Programmable ClockOutput In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 10).
Figure 10.
AT89C51IC2 Table 24. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
Table 25. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51IC2 Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
Figure 11. PCA Timer/Counter To PCA modules Fclk periph /6 overflow Fclk periph / 2 CH T0 OVF It CL 16 bit up counter P1.
AT89C51IC2 Table 26. CMOD Register CMOD - PCA Counter Mode Register (D9h) 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable 6 WDTE Cleared to disable Watchdog Timer function on PCA Module 4. Set to enable Watchdog Timer function on PCA Module 4.
Table 27. CCON Register CCON - PCA Counter Control Register (D8h) 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description PCA Counter Overflow flag 7 CF Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit 6 CR Must be cleared by software to turn the PCA counter off.
AT89C51IC2 Figure 12. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt priority decoder Module 2 Module 3 Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IEN0.6 EC IEN0.7 EA PCA Modules: each one of the five compare/capture modules has six possible functions.
Table 28 shows the CCAPMn settings for the various PCA functions. Table 28.
AT89C51IC2 Table 29. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function 0 0 0 0 0 0 0 No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer / Compare mode.
Table 31.
AT89C51IC2 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH).
Figure 14. PCA Compare Mode and PCA Watchdog Timer CCON CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16 bit comparator CH RESET * CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA to 0xDE CMOD 0xD9 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
AT89C51IC2 Figure 15. PCA High Speed Output Mode CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Write to CCA PnL Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable 16 bit comparator CH Match CL CEXn PCA counter/timer ECO Mn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.
Figure 16. PCA PWM Mode CCAPnH Overflow CCAPnL “0” CEXn Enable 8 bit comparator “1” CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog.
AT89C51IC2 Serial I/O Port The serial I/O port in the AT89C51IC2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3).
Figure 19. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit D2 D3 D4 D5 Data byte D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
AT89C51IC2 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
Table 35. SADDR Register SADDR - Slave Address Register (A9h) 7 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for UART for mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 20. Baud Rate selection TIMER1 TIMER_BRG_RX 0 TIMER2 0 1 / 16 Rx Clock 1 RCLK RBCK INT_BRG TIMER1 0 TIMER2 1 TIMER_BRG_TX 0 / 16 1 Tx Clock TCLK TBCK INT_BRG Table 36.
AT89C51IC2 Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Figure 21.
Table 37. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit.
AT89C51IC2 Table 38. Example of computed value when X2=1, SMOD1=1, SPD=1 Baud Rates FOSCA = 16.384 MHz FOSCA = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Table 39. Example of computed value when X2=0, SMOD1=0, SPD=0 Baud Rates FOSCA = 16.384 MHz FOSCA = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.
UART Registers Table 40. SADEN Register SADEN - Slave Address Mask Register for UART (B9h) 7 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Table 41. SADDR Register SADDR - Slave Address Register for UART (A9h) 7 6 5 4 Reset Value = 0000 0000b Table 42. SBUF Register SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 Reset Value = XXXX XXXXb Table 43.
AT89C51IC2 Table 44. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
Table 45. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - Description Serial port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51IC2 Table 46. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator.
Interrupt System The AT89C51IC2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Two Wire Interface (I2C) interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 22. Figure 22.
AT89C51IC2 Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 0043H, the I2C interrupt vector at 0043H and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 devices. Table 47. Priority Level Bit Values IPH.x IPL.
Table 48. IENO Register IEN0 - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA 6 EC Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit Cleared to disable. Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Cleared to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt.
AT89C51IC2 Table 49. IPL0 Register IPL0 - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - PPCL PT2L PSL PT1L PX1L PT0L PX0L Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPCL PCA interrupt Priority bit Refer to PPCH for priority level. 5 PT2L Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PSL Serial port Priority bit Refer to PSH for priority level.
Table 50. IPH0 Register IPH0 - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. PPCH PCA interrupt Priority high bit.
AT89C51IC2 Table 51. IEN1 Register IEN1 - Interrupt Enable Register (B1h) 7 6 5 4 3 2 1 0 - - - - - ESPI ETWI KBD Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 ESPI SPI interrupt Enable bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt. Set to enable TWI interrupt.
Table 52. IPL1 Register IPL1 - Interrupt Priority Register (B2h) 7 6 5 4 3 2 1 0 - - - - - SPIL TWIL KBDL Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
AT89C51IC2 Table 53. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) 7 6 5 4 3 2 1 0 - - - - - SPIH TWIH KBDH Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
Interrupt Sources and Vector Addresses 66 Table 54.
AT89C51IC2 Power Management Two power reduction modes are implemented in the AT89C51IC2: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Enhanced Features”. Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an high level has to be applied on the RST pin.
Table 1. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor(1) VDD Rise Time Oscillator Start-Up Time 1 ms 10 ms 100 ms 5 ms 820 nF 1.2 µF 12 µF 20 ms 2.7 µF 3.9 µF 12 µF Note: These values assume VDD starts from 0V to the nominal value. If the time between 2 on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence.
AT89C51IC2 Reset Recommendation to Prevent Flash Corruption An example of bad initialization situation may occur in an instance where the bit ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since this bit allows mapping of the bootloader in the code area, a reset failure can be critical. If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet due to a bad reset) the bit ENBOOT in SFRs may be set.
Figure 25. Power-down Exit Waveform INT0 INT1 XTALA or XTALB Active Phase Power-down Phase Oscillator Restart Phase Active Phase Exit from Power-down by reset redefines all the SFRs, exit from Power-down by external interrupt does no affect the SFRs. Exit from Power-down by either reset or external interrupt does not affect the internal RAM content.
AT89C51IC2 Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
drive the network. The Master may select each Slave device by software through port pins (Figure 27). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
AT89C51IC2 Functional Description Figure 27 shows a detailed structure of the SPI Module. Figure 27.
Figure 28. Full-Duplex Master-Slave Interconnection 8-bit Shift register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU 8-bit Shift register SCK VDD SS VSS Slave MCU Master Mode The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT).
AT89C51IC2 Figure 29. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 30.
Error Conditions The following flags in the SPSTA signal SPI error conditions: Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated • The SPEN bit in SPCON is cleared.
AT89C51IC2 Figure 32. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS Registers There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs.
Bit Number Bit Mnemonic SPR1 1 0 SPR0 Description SPR2 SPR1 0 0 SPR0 Serial Peripheral Rate 0 FCLK PERIPH /2 0 0 1 FCLK PERIPH /4 0 1 0 FCLK PERIPH /8 0 1 1 FCLK PERIPH /16 1 0 0 FCLK PERIPH /32 1 0 1 FCLK PERIPH /64 1 1 0 FCLK PERIPH /128 1 1 1 Invalid Reset Value = 0001 0100b Not bit addressable Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions: • Data transfer complete • Write colli
AT89C51IC2 Bit Number Bit Mnemonic Description 1 - 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable Serial Peripheral DATa Register (SPDAT) The Serial Peripheral Data Register (Table 60) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model.
Keyboard Interface The AT89C51IC2 implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes.
AT89C51IC2 Registers Table 61. KBF Register KBF-Keyboard Flag Register (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description KBF7 Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set. Must be cleared by software. KBF6 Keyboard line 6 flag Set by hardware when the Port line 6 detects a programmed level.
Table 62. KBE Register KBE-Keyboard Input Enable Register (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic Description 7 KBE7 Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request.
AT89C51IC2 Table 63. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6. Set to enable a high level detection on Port line 6.
2-wire Interface (TWI) This section describes the 2-wire interface. In the rest of the section SSLC means Twowire. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 400Kbit/s in standard mode.
AT89C51IC2 Figure 36. Block Diagram 8 Address Register SSADR Comparator Input Filter SDA PI2.1 Output Stage SSDAT ACK Shift Register Arbitration & Sink Logic Input Filter SCL PI2.
Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 73), the Synchronous Serial Data register (SSDAT; Table 74), the Synchronous Serial Control and Status register (SSCS; Table 75) and the Synchronous Serial Address register (SSADR Table 78).
AT89C51IC2 R : Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 38 to Figure 41, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer.
When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each of these status code is detailed in Table 69. This scheme is repeated until a STOP condition is transmitted.
AT89C51IC2 slave address followed by the data direction bit which must be at logic 1 (R) for SSLC to operate in the slave transmitter mode. After its own slave address and the R bit have been received, the serial interrupt flag is set and a valid status code can be read from SSCS. This status code is used to vector to an interrupt service routine. The appropriate action to be taken for each of these status code is detailed in Table 71.
Figure 38.
AT89C51IC2 Table 68.
Figure 39.
AT89C51IC2 Table 69. Status in master receiver mode Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware 08h A START condition has Write SLA+R been transmitted X 0 0 X Write SLA+R X 0 0 X 10h A repeated START condition has been transmitted Write SLA+W X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode.
Figure 40. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. S SLA W Data A 60h A Data 80h Last data byte received is not acknowledged. A P or S 80h A0h A P or S 88h Arbitration lost as master and addressed as slave A 68h Reception of the general call address and one or more data bytes. General Call Data A 70h Last data byte received is not acknowledged.
AT89C51IC2 Table 70.
Application Software Response Status Code (SSCS) 98h To/from SSDAT Status of the 2-wire bus and 2-wire hardware Previously addressed with general call; data has been received; NOT ACK has been returned STA A0h SI AA 0 0 0 0 Read data byte or 0 0 0 1 Read data byte or 1 1 0 0 0 0 1 0 0 No SSDAT action or 0 0 0 1 1 0 0 0 0 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=logic 1 Switched to the not addressed slave mode; ow
AT89C51IC2 Figure 41. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes SLA A R Data A A8h Arbitration lost as master and addressed as slave B8h Data A P or S C0h A B0h Last data byte transmitted.
Application Software Response Status Code (SSCS) C0h To/from SSDAT Status of the 2-wire bus and 2-wire hardware Data byte in SSDAT has been transmitted; NOT ACK has been received To SSCON STA Last data byte in SSDAT has been transmitted (AA=0); ACK has been received SI AA No SSDAT action or 0 0 0 0 No SSDAT action or 0 0 0 1 No SSDAT action or No SSDAT action C8h STO 1 1 0 0 0 0 1 Switched to the not addressed slave mode; own SLA will be recognised; GCA will be recognised if GC=
AT89C51IC2 Registers Table 73. SSCON Register SSCON - Synchronous Serial Control register (93h) 7 6 5 4 3 2 1 0 CR2 SSIE STA STO SI AA CR1 CR0 Bit Number Bit Mnemonic Description 7 CR2 Control Rate bit 2 See Table 67. 6 SSIE Synchronous Serial Interface Enable bit Clear to disable SSLC. Set to enable SSLC. 5 STA Start flag Set to send a START condition on the bus. 4 ST0 Stop flag Set to send a STOP condition on the bus.
Bit Number Bit Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 75. SSCS (094h) read - Synchronous Serial Control and Status Register 7 6 5 4 3 2 1 0 SC4 SC3 SC2 SC1 SC0 0 0 0 Table 76. SSCS Register: Read Mode - Reset Value = F8h Bit Number 100 Bit Mnemonic Description 0 0 Always zero 1 0 Always zero 2 0 Always zero 3 SC0 4 SC1 5 SC2 Status Code bit 2 See Table 68.to Table 72.
AT89C51IC2 Table 77. SSADR (096h) - Synchronus Serial Address Register (read/write) 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 Table 78. SSADR Register - Reset value = FEh Bit Number Bit Mnemonic Description 7 A7 Slave Address bit 7 6 A6 Slave Address bit 6 5 A5 Slave Address bit 5 4 A4 Slave Address bit 4 3 A3 Slave Address bit 3 2 A2 Slave Address bit 2 1 A1 Slave Address bit 1 0 GC General Call bit Clear to disable the general call address recognition.
Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
AT89C51IC2 Table 80. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Number Bit Mnemonic Description 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Reserved The value read from this bit is undetermined. Do not try to set this bit. S2 0 0 0 0 1 1 1 1 S1 S0Selected Time-out 00 (214 - 1) machine cycles, 16.
Power-off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (Table 81). POF is set by hardware when VCC rises from 0 to its nominal voltage.
AT89C51IC2 ONCE(TM) Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using AT89C51IC2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C51IC2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated.
Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches.
AT89C51IC2 Flash EEPROM Memory The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 32K Bytes of program memory organized in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.
Flash Registers and Memory Map Hardware Register The AT89C51IC2 Flash memory uses several registers for its management: • Hardware registers can only be accessed through the parallel programming modes which are handled by the parallel programmer. • Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space.
AT89C51IC2 Table 85. Program Lock Bits Program Lock Bits Security Level LB0 LB1 LB2 1 U U U No program lock features enabled. Protection Description 2 P U U MOVC instruction executed from external program memory is disabled from fetching code Bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. ISP and software programming with API are still allowed.
Table 86.
AT89C51IC2 Table 88. Program Lock Bits of the SSB Program Lock Bits Security level LB0 LB1 1 U U No program lock features enabled. 2 P U ISP programming of the Flash is disabled. 3 X P Same as 2, also verify through ISP programming interface is disabled. Note: Flash Memory Status Protection Description U: unprogrammed or "one" level. P: programmed or "zero" level. X: don’t care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
Bootloader Architecture Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 43.
AT89C51IC2 Functional Description Figure 44. Bootloader Functional Description Exernal Host with Specific Protocol Communication User Application User Call Management (API ) ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on-chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device.
Bootloader Functionality Introduction The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’s code but can be manually forced into default ISP operation.
AT89C51IC2 Boot Process Figure 46.
ISP Protocol Description Physical Layer Frame Description The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 1 bit • Flow control: none • Baud rate: autobaud is performed by the bootloader to compute the baud rate choosen by the host. The Serial Protocol is based on the Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below. Table 89.
AT89C51IC2 Functional Description Software Security Bits (SSB) The SSB protects any Flash access from ISP command. The command "Program Software Security bit" can only write a higher priority level. There are three levels of security: • level 0: NO_SECURITY (FFh) This is the default level. From level 0, one can write level 1 or level 2. • level 1: WRITE_SECURITY (FEh ) For this level it is impossible to write in the Flash memory, BSB and SBV. The Bootloader returns ’P’ on write access.
Full Chip Erase The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some Bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. Checksum Error When a checksum error is detected send ‘X’ followed with CR&LF. Flow Description Overview An initialization step must be performed after each Reset.
AT89C51IC2 Autobaud Performances The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51IC2 to establish the baud rate.
Figure 48.
AT89C51IC2 Example Programming Data (write 55h at address 0010h in the Flash) HOST : 01 0010 00 55 9A BOOTLOADER : 01 0010 00 55 9A . CR LF Programming Atmel function (write SSB to level 2) HOST : 02 0000 03 05 01 F5 BOOTLOADER : 02 0000 03 05 01 F5. CR LF Writing Frame (write BSB to 55h) HOST : 03 0000 03 06 00 55 9F BOOTLOADER : 03 0000 03 06 00 55 9F .
Blank Check Command Description Figure 50. Blank Check Flow Bootloader Host Blank Check Command Send Blank Check Command Wait Blank Check Command OR Checksum error ’X’ & CR & LF Wait Checksum Error Send Checksum error COMMAND ABORTED Flash blank OR ’.
AT89C51IC2 Display Data Description Figure 51.
Example Display data from address 0000h to 0020h Read Function HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF (16 data) BOOTLOADER 0010=-----data------ CR LF (16 data) BOOTLOADER 0020=data CR LF ( 1 data) This flow is similar for the following frames: • Reading Frame • EOF Frame/Atmel Frame (only reading Atmel Frame) Description Figure 52.
AT89C51IC2 ISP Commands Summary Table 92. ISP Commands Summary Command Command Name Data[0] Data[1] Command Effect Program Nb Data Byte. 00h Bootloader will accept up to 128 (80h) data Bytes. The data Bytes should be 128 Byte page Flash boundary.
API Call Description Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FFF0h. Results are returned in the registers.
AT89C51IC2 Table 93. API Call Summary (Continued) Command R1 A DPTR0 DPTR1 Returned Value Command Effect PROGRAM DATA PAGE 09h Number of byte to program Address of the first byte to program in the Flash memory Address in XRAM of the first data to program ACC = 0: DONE Remark: number of bytes to program is limited such as the Flash write remains in a single 128 bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or, 80h.
Electrical Characteristics Absolute Maximum Ratings Note: C = commercial......................................................0°C to 70°C I = industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC to VSS .......................................-0.5V to + 6.5V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation ................................................
AT89C51IC2 TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution) VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued) Symbol Parameter Min Typ Max Unit Test Conditions VCC = 5V ± 10% VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3 V IOH = -200 µA VCC - 0.7 V IOH = -3.2 mA VCC - 1.5 V IOH = -7.0 mA 0.9 VCC V VCC = 2.7V to 5.
DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0to 48 MHz TA = -40°C to +85°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0 to 48 MHz Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage except RST, XTAL1 VIH1 Input High Voltage, RST, XTAL1 VOL Typ Max Unit Test Conditions -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V Output Low Voltage, ports 1, 2, 3, 4(6) 0.45 V IOL = 0.
AT89C51IC2 If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Icc Flash Write operation current while an on-chip flash page write is on going. Figure 53. ICC Test Condition, Active Mode VCC ICC VCC VCC P0 VCC RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 54.
AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low.
AT89C51IC2 Table 95. AC Parameters for a Fix Clock Symbol -M -L Min Max Min Units Max T 25 25 ns TLHLL 35 35 ns TAVLL 5 5 ns TLLAX 5 5 ns TLLIV n 65 65 ns TLLPL 5 5 ns TPLPH 50 50 ns TPLIV 30 TPXIX 30 0 0 ns ns TPXIZ 10 10 ns TAVIV 80 80 ns TPLAZ 10 10 ns Table 96. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X Parameter for M Range X Parameter for -L Range Units TLHLL Min 2T-x T-x 15 15 ns TAVLL Min T-x 0.
External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN PORT 0 TLLAX TAVLL INSTR IN TPLIV TPLAZ A0-A7 TPXIX TPXAV TPXIZ INSTR IN A0-A7 INSTR IN TAVIV PORT 2 ADDRESS OR SFR-P2 External Data Memory Characteristics ADDRESS A8-A15 Table 97.
AT89C51IC2 Table 98.
Symbol Type Standard Clock X2 Clock X Parameter for M Range X Parameter for L Range Units TRLRH Min 6T-x 3T-x 25 25 ns TWLWH Min 6T-x 3T-x 25 25 ns TRLDV Max 5T-x 2.5 T - x 30 30 ns TRHDX Min x x 0 0 ns TRHDZ Max 2T-x T-x 25 25 ns TLLDV Max 8T-x 4T -x 45 45 ns TAVDV Max 9T-x 4.5 T - x 65 65 ns TLLWL Min 3T-x 1.5 T - x 30 30 ns TLLWL Max 3T+x 1.5 T + x 30 30 ns TAVWL Min 4T-x 2T-x 30 30 ns TQVWX Min T-x 0.
AT89C51IC2 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TRHDX A0-A7 DATA IN TRLAZ TAVWL PORT 2 ADDRESS OR SFR-P2 Serial Port Timing - Shift Register Mode ADDRESS A8-A15 OR SFR P2 Table 99.
Shift Register Timing Waveforms INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA 0 1 2 3 4 5 6 7 TXHDX TXHDV VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI External Clock Drive Waveforms VALID VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCHCX TCLCH TCLCX TCLCL AC Testing Input/Output Waveforms VCC -0.5V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45 V AC inputs during testing are driven at VCC - 0.
AT89C51IC2 Figure 57.
Ordering Information Table 102.
AT89C51IC2 Package Drawing PLCC44 141 4301D–8051–02/08
Package Drawing VQFP44 142 AT89C51IC2 4301D–8051–02/08
AT89C51IC2 Datasheet Revision History Changes from Rev. A 01/04 - Rev. B 01/06 1. Added green product ordering information. Changes from Rev. B 01/06 - Rev. C 06/06 1. Correction to ordering information concerning product marking on green products. Changes from Rev. C 06/06 - Rev. D 02/08 1. Removed non green part numbers from ordering information.
Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ...................................................
AT89C51IC2 Interrupt Sources and Vector Addresses............................................................ 66 Power Management ............................................................................ 67 Reset .................................................................................................................. Reset Recommendation to Prevent Flash Corruption ........................................ Idle Mode ................................................................................
DC Parameters for Low Voltage ....................................................................... 130 AC Parameters ................................................................................................. 132 Ordering Information ........................................................................ 140 Package Drawing .............................................................................. 141 PLCC44 .....................................................................................
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