Datasheet

97
4235K–8051–05/08
AT89C51RD2/ED2
Table 24-5. User Memory Lock Bits of the SSB
Note: X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash verification.
24.4 Flash Memory Status
AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader.
After ISP or parallel programming, the possible contents of the Flash memory are summarized in
Figure 24-1:
Figure 24-1. Flash Memory Possible Contents
24.5 Memory Organization
When the EA pin is high, the processor fetches instructions from internal program Flash. If the
EA pin is tied low, all program memory fetches are from external memory.
24.6 Bootloader Architecture
24.6.1 Introduction
The bootloader manages communication according to a specifically defined protocol to provide
the whole access and service on Flash memory. Furthermore, all accesses and routines can be
called from the user application.
Program Lock Bits
Protection Description
Security
Level LB0 LB1
1 1 1 No program lock features enabled.
2 0 1 ISP programming of the Flash is disabled.
3 X 0 Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
Default After ISP
After Parallel
Programming
After Parallel
Programming
After Parallel
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP
Dedicated
ISP
Application
Virgin
or
Application
Virgin
or
Application
FFFFh