Datasheet

4235K–8051–05/08

AT89C51RD2/ED2

24.3 Flash Registers and Memory Map

The AT89C51RD2/ED2 Flash memory uses several registers for its management:

• Hardware register can only be accessed through the parallel programming modes which are

handled by the parallel programmer.

• Software registers are in a special page of the Flash memory which can be accessed through

the API or with the parallel programming modes. This page, called "Extra Flash Memory", is

not in the internal Flash program memory addressing space.

24.3.1 Hardware Register

The only hardware register of the AT89C51RD2/ED2 is called Hardware Byte or Hardware

Security Byte (HSB).

Table 24-1. Hardware Security Byte (HSB)

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

• When this bit is programmed (‘0’ value) the boot address is F800h.

• When this bit is unprogrammed (‘1’ value) the boot address is 0000h.

By default, this bit is programmed and the ISP is enabled.

24.3.2 Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data when pro-

grammed as shown in Table 24-2.

7 6 5 4 3 2 1 0

X2 BLJB - - XRAM LB2 LB1 LB0

Bit

Number

Bit

Mnemonic Description

7 X2

X2 Mode

Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.

Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset (Default).

6 BLJB

Boot Loader Jump Bit

Unprogrammed (‘1’ value) to start the user’s application on next reset at address 0000h.

Programmed (‘0’ value) to start the boot loader at address F800h on next reset (Default).

5 - Reserved

4 -

Reserved

3 XRAM

XRAM config bit (only programmable by programmer tools)

Programmed to inhibit XRAM.

Unprogrammed, this bit to valid XRAM (Default).

2-0 LB2-0

User Memory Lock Bits (only programmable by programmer tools)

See Table 24-2