Datasheet

87
4235K–8051–05/08
AT89C51RD2/ED2
21. Power-off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
CC
switch-on. A warm start reset occurs while V
CC
is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (Table 21-1). POF is set by hardware
when V
CC
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
ing the user to determine the type of reset.
Table 21-1. PCON Register
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Cleared by software to recognize the next reset type.
Set by hardware when V
CC
rises from 0 to its nominal voltage. Can also be set by
software.
3 GF1
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
2 GF0
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
1 PD
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.