Datasheet

70
4235K–8051–05/08
AT89C51RD2/ED2
Reset Value = 0001 0100b
Not bit addressable
16.3.5.2 Serial Peripheral Status Register (SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 16-4 describes the SPSTA register and explains the use of every bit in the register.
Table 16-4. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
4 MSTR
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
3 CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
2 CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
1
SPR1
SPR2 SPR1 SPR0 Serial Peripheral Rate
0 0 1 F
CLK PERIPH
/2
0 0 1 F
CLK PERIPH
/4
0 1 0 F
CLK PERIPH
/8
0 1 1F
CLK PERIPH
/16
1 0 0F
CLK PERIPH
/32
1 0 1F
CLK PERIPH
/64
1 1 0F
CLK PERIPH
/128
1 1 1Invalid
SPR0
Bit Number Bit Mnemonic Description
7 6 5 4 3 2 1 0
SPIF WCOL SSERR MODF - - - -
Bit Number
Bit
Mnemonic Description
7 SPIF
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6 WCOL
Write Collision Flag
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.