Datasheet

64
4235K–8051–05/08
AT89C51RD2/ED2
16.2.3 SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out of the devices through
their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to
exchange one Byte on the serial lines.
16.2.4 Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any
message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
The Master may select each Slave device by software through port pins (Figure 16-2). To pre-
vent bus conflicts on the MISO line, only one slave should be selected at a time by the Master
for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI
Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error
conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of
configuration can be found when only one Master is driving the network and there is no way
that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be
set
(1)
.
• The Device is configured as a Slave with CPHA and SSDIS control bits set
(2)
. This kind of
configuration can happen when the system comprises one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master uses
the SS pin to select the communicating Slave device.
Note: 1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this
mode, the SS is used to start the transmission.
16.2.5 Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is controlled by
three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one
of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.
Table 16-1 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 16-1. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
0 0 0 F
CLK PERIPH
/2 2
0 0 1 F
CLK PERIPH
/4 4
0 1 0 F
CLK PERIPH
/8 8
0 1 1 F
CLK PERIPH
/16 16
1 0 0 F
CLK PERIPH
/32 32
1 0 1 F
CLK PERIPH
/64 64
1 1 0 F
CLK PERIPH
/128 128
1 1 1 Don’t Use No BRG