Datasheet

58
4235K–8051–05/08
AT89C51RD2/ED2
Table 14-13. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
Reset Value = XXX0 0000b
Not bit addressable
7 6 5 4 3 2 1 0
- - - BRR TBCK RBCK SPD SRC
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3 TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2 RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0 SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select F
OSC
/12 as the Baud Rate Generator (F
CLK PERIPH
/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.