Datasheet

52
4235K–8051–05/08
AT89C51RD2/ED2
Table 14-3. Baud Rate Selection Table UART
14.4.1 Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG
overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON
register and the value of the SMOD1 bit in PCON register.
Figure 14-5. Internal Baud Rate
• The baud rate for UART is token by formula:
TCLK
(T2CON)
RCLK
(T2CON)
TBCK
(BDRCON)
RBCK
(BDRCON)
Clock Source
UART Tx
Clock Source
UART Rx
0 0 0 0 Timer 1 Timer 1
1 0 0 0 Timer 2 Timer 1
0 1 0 0 Timer 1 Timer 2
1 1 0 0 Timer 2 Timer 2
X 0 1 0 INT_BRG Timer 1
X 1 1 0 INT_BRG Timer 2
0 X 0 1 Timer 1 INT_BRG
1 X 0 1 Timer 2 INT_BRG
X X 1 1 INT_BRG INT_BRG
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
F
Clk Periph
÷ 6
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2
INT_BRG
Baud_Rate =
6
(1-SPD)
⋅ 32 ⋅ (256 -BRL)
2
SMOD1
⋅ F
PER
BRL = 256 -
6
(1-SPD)
⋅ 32 ⋅ Baud_Rate
2
SMOD1
⋅ F
PER