Datasheet

4235K–8051–05/08

AT89C51RD2/ED2

14. Serial I/O Port

The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a Univer-

sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and

3). Asynchronous transmission and reception can occur simultaneously and at different baud

rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

14.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To

enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 14-

1).

Figure 14-1. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.

An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by

two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table

14-4.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only soft-

ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear

FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure

14-2. and Figure 14-3.).

Figure 14-2. UART Timings in Mode 1

RITIRB8TB8RENSM2SM1SM0/FE

IDLPDGF0GF1POF-SMOD0SMOD1

To UART framing error control

SM0 to UART mode control (SMOD0 = 0)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SCON (98h)

PCON (87h)

Data byte

SMOD0=X

Stop

bit

Start

bit

RXD

D7D6D5D4D3D2D1D0

SMOD0=1