Datasheet

16
4235K–8051–05/08
AT89C51RD2/ED2
6.2 Functional Block Diagram
Figure 6-1. Functional Oscillator Block Diagram
6.2.1 Prescaler Divider
• A hardware RESET puts the prescaler divider in the following state:
• CKRL = FFh: F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard C51 feature)
• Any value between FFh down to 00h can be written by software into CKRL register in order to
divide frequency of the selected oscillator:
• CKRL = 00h: minimum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/1020 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/510 (X2 Mode)
• CKRL = FFh: maximum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
(X2 Mode)
F
CLK CPU
and F
CLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xFF then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
F
OSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
F
CPU
F =
CLKP ERIPH
F
OSC
2 255 CKRL–( )×
-----------------------------------------------=
F
CPU
F =
CLKP ERIPH
F
OSC
4 255 CKRL–( )×
-----------------------------------------------=