Datasheet

122
4235K–8051–05/08
AT89C51RD2/ED2
25.3.6 External Data Memory Read Cycle
25.3.7 Serial Port Timing - Shift Register Mode
Table 25-7. Symbol Description
Table 25-8. AC Parameters for a Fix Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
LLAX
T
AVDV
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid
Symbol
-M
UnitsMin Max
T
XLXL
300 ns
T
QVHX
200 ns
T
XHQX
30 ns
T
XHDX
0 ns
T
XHDV
117 ns