Datasheet

96
4235K–8051–05/08
AT89C51RD2/ED2
After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica-
tion to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 24-4 and Table 24-5.
To assure code protection from a parallel access, the HSB must also be at the required level.
Table 24-4. Software Security Byte
The two lock bits provide different levels of protection for the on-chip code and data, when pro-
grammed as shown in Table 24-5.
BSB Boot Status Byte 0FFh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h Atmel
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: Memories Size and
Type
ECh AT89C51RD2/ED2 64KB
Copy of the Device ID #3: Name and Revision EFh
AT89C51RD2/ED2 64KB,
Revision 0
7 6 5 4 3 2 1 0
- - - - - - LB1 LB0
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
Do not clear this bit.
6 -
Reserved
Do not clear this bit.
5 -
Reserved
Do not clear this bit.
4 -
Reserved
Do not clear this bit.
3 -
Reserved
Do not clear this bit.
2 -
Reserved
Do not clear this bit.
1-0 LB1-0
User Memory Lock Bits
See Table 24-5
Mnemonic Definition Default value Description