Datasheet

4235K–8051–05/08

AT89C51RD2/ED2

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been

completed. SPIF bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent

with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt

requests. When SSDIS is set, no MODF interrupt request is generated.

Figure 16-7 gives a logical view of the above statements.

Figure 16-7. SPI Interrupt Requests Generation

16.3.5 Registers

There are three registers in the Module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

16.3.5.1 Serial Peripheral Control Register (SPCON)

• The Serial Peripheral Control Register does the following:

• Selects one of the Master clock rates

• Configure the SPI Module as Master or Slave

• Selects serial clock polarity and phase

• Enables the SPI Module

• Frees the SS pin for a general-purpose

Table 16-3 describes this register and explains the use of each bit

Table 16-3. SPCON Register

SPCON - Serial Peripheral Control Register (0C3H)

SSDIS

MODF

CPU Interrupt Request

SPI Receiver/error

CPU Interrupt Request

SPI Transmitter

SPI

CPU Interrupt Request

SPIF

7 6 5 4 3 2 1 0

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit Number Bit Mnemonic Description

7 SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate.

6 SPEN

Serial Peripheral Enable

Cleared to disable the SPI interface.

Set to enable the SPI interface.

5 SSDIS

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode, this bit

has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request

is generated