Datasheet

82
AT89C51CC03
4182O–CAN–09/08
Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 42. Machine Cycle Count
To compute WD Time-Out, the following formula is applied:
Note: Svalue represents the decimal value of (S2 S1 S0)
The following table outlines the time-out value for Fosc
XTAL
= 12 MHz in X1 mode
Table 43. Time-Out Computation
S2 S1 S0 Machine Cycle Count
000 2
14
001 2
15
010 2
16
011 2
17
100 2
18
101 2
19
110 2
20
111 2
21
S2 S1 S0 Fosc = 12 MHz Fosc = 16 MHz Fosc = 20 MHz
0 0 0 16.38 ms 12.28 ms 9.82 ms
0 0 1 32.77 ms 24.57 ms 19.66 ms
0 1 0 65.54 ms 49.14 ms 39.32 ms
0 1 1 131.07 ms 98.28 ms 78.64 ms
1 0 0 262.14 ms 196.56 ms 157.28 ms
1 0 1 524.29 ms 393.12 ms 314.56 ms
1 1 0 1.05 s 786.24 ms 629.12 ms
1 1 1 2.10 s 1.57 s 1.25 s
FTime Out
F
osc
62×
WDX2 X2∧
2
14
2
Svalue
×()
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