Datasheet

57
AT89C51CC03
4182O–CAN–09/08
Table 22. Read MOVC A, @DPTR
Code Execution
FCON Register
ENBOOT DPTR FM1 FM0 XROW
Hardware
Byte
External
CodeFMOD1 FMOD0 FPS
From FM0
00X
0 0000h to FFFFh OK
1
0000h to F7FF OK
F800h to FFFFh Do not use this configuration
01X X
0000 to 007Fh
See
(1)
OK
10X X X OK
11X
0 000h to FFFFh OK
1
0000h to F7FF OK
F800h to FFFFh Do not use this configuration
From FM1
(ENBOOT =1
00
0
1
0000h to F7FF OK
F800h to FFFFh OK
0X NA
1
1X OK
0X NA
01X
1
0000h to 007h
See
(2)
OK
0NA
10X
1
X
OK
0NA
11X
1
000h to FFFFh
OK
0NA
External code :
EA=0 or Code
Roll Over
X0X X X OK
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh