Datasheet

181
AT89C51CC03
4182O–CAN–09/08
Timings Test conditions: capacitive load on all pins= 60 pF.
Note: 1. Value of this parameter depends on prescacler ratio defined in bits 0,1 and 7 of SCON Register.In the above table, the ratio
used is 4. As it can be set also to 8, 16, 32, 64 or 128, the factor of
T
PER
must be changed according to the new ratio.E.g.
2TPER-20ns(1) will be changed to 4TPER-20ns(1) if the prescaler ratio equals 8.
Table 1. SPI Interface Master AC Timing
V
DD
= 2.7 to 3.3 V, T
A
= -40 to +85°C
Symbol Parameter Min Max Unit
Slave Mode
T
CHCH
Clock Period 6
(1)
T
PER
T
CHCX
Clock High Time 3
(1)
T
PER
T
CLCX
Clock Low Time 3
(1)
T
PER
T
SLCH
, T
SLCL
SS Low to Clock edge 4T
PER
-20ns
(1)
ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 50 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 50 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 50 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
CLSH
, T
CHSH
SS High after Clock Edge 4T
PER
+20ns
(1)
ns
T
SLOV
SS Low to Output Data Valid
4T
PER
+20ns
(1)
ns
T
SHOX
Output Data Hold after SS High
2T
PER
+100ns
(1)
ns
T
SHSL
SS High to SS Low
2T
PER
+120ns
(1)
T
OLOH
Output Rise time 100 ns
T
OHOL
Output Fall Time 100 ns
Master Mode
T
CHCH
Clock Period 4
(1)
T
PER
T
CHCX
Clock High Time
2T
PER
-20ns
(1)
T
PER
T
CLCX
Clock Low Time 2T
PER
-20ns
(1)
T
PER
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 50 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 0 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 20 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
CLCH
Output Data Rise time 100 ns
T
CHCL
Output Data Fall Time 100 ns