Datasheet

165
AT89C51CC03
4182O–CAN–09/08
Table 113. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value = XXXX 0000b
bit addressable
76543210
----SPILPOVRLPADCL PCANL
Bit
Number
Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3SPIL
SPI Interrupt Priority Level Less Significant Bit
Refer to SPIH for priority level.
2POVRL
Timer Overrun Interrupt Priority Level Less Significant Bit
Refer to PI2CH for priority level.
1PADCL
ADC Interrupt Priority Level Less Significant Bit
Refer to PSPIH for priority level.
0PCANL
CAN Interrupt Priority Level Less Significant Bit
Refer to PKBH for priority level.