Datasheet

158
AT89C51CC03
4182O–CAN–09/08
Table 105. ADCLK Register
ADCLK (S:F2h)
ADC Clock Prescaler
Reset Value = XXX0 0000b
Note: 1. In X1 mode:
For PRS > 0 F
ADC
= FXTAL
4xPRS
For PRS = 0 F
ADC
= FXTAL
128
In X2 mode:
For PRS > 0 F
ADC
= FXTAL
2xPRS
For PRS = 0 F
ADC
= FXTAL
64
Table 106. ADDH Register
ADDH (S:F5h Read Only)
ADC Data High Byte Register
Reset Value = 00h
Table 107. ADDL Register
ADDL (S:F4h Read Only)
ADC Data Low Byte Register
76543210
- - - PRS 4PRS 3PRS 2PRS 1PRS 0
Bit
Number
Bit
Mnemonic Description
7-5 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
4-0 PRS4:0
Clock Prescaler
See Note
(1)
76543210
ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2
Bit
Number
Bit
Mnemonic Description
7-0 ADAT9:2
ADC result
bits 9-2
76543210
------ADAT 1ADAT 0