Datasheet

139
AT89C51CC03
4182O–CAN–09/08
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 94) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 94. SPDAT Register
SPDAT - Serial Peripheral Data Register (0D6H)
Reset Value = Indeterminate
R7:R0: Receive data bits
4MODF
Mode Fault
- Set by hardware to indicate that the SS
pin is in inappropriate logic level (in both
master and slave modes).
- Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS
remains high.
A new transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN
bit in SPCON register).
3 SPTE
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be
loaded with another data).
- Cleared by hardware when transmit register is full (no more data should be
loaded in SPDAT).
2UARTM
Serial Peripheral UART mode
Set and cleared by software:
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
1SPTEIE
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag
goes high. To enable SPIF interrupt again, SPTEIE should be cleared.
0MODFIE
Interrupt Enable for MODF
Set and cleared by software:
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
Bit
Number
Bit
Mnemonic Description
76543210
R7 R6 R5 R4 R3 R2 R1 R0