Datasheet

138
AT89C51CC03
4182O–CAN–09/08
Reset Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
and Control (SPSCR)
The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS
pin (mode fault error)
Table 93. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (0D5H)
3CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle state.
2CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle
state (see CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
1 SPR1
SPR2
SPR1 SPR0 Serial Peripheral Rate
0 0 0 Invalid
00 1 F
CLK PERIPH
/4
01 0 F
CLK PERIPH
/8
01 1F
CLK PERIPH
/16
10 0F
CLK PERIPH
/32
10 1F
CLK PERIPH
/64
11 0F
CLK PERIPH
/128
1 1 1 Invalid
0 SPR0
Bit Number Bit Mnemonic Description
76543210
SPIF - OVR MODF SPTE UARTM SPTEIE MODFIE
Bit
Number
Bit
Mnemonic Description
7SPIF
Serial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5OVR
Overrun Error Flag
- Set by hardware when a byte is received whereas SPIF is set (the previous
received data is not overwritten).
- Cleared by hardware when reading SPSCR