Datasheet

118
AT89C51CC03
4182O–CAN–09/08
Table 65. CANSTCH Register
CANSTCH (S:B2h)
CAN Message Object Status Register
Note: See Figure 50.
No default value after reset.
76543210
DLCW TXOK RXOK BERR SERR CERR FERR AERR
Bit
Number Bit Mnemonic Description
7DLCW
Data Length Code Warning
The incoming message does not have the DLC expected. Whatever the frame
type, the DLC field of the CANCONCH register is updated by the received
DLC.
6TXOK
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more message objects
are enabled as producers, the lower index message object (0 to 13) is
supplied first.
This flag can generate an interrupt.
5RXOK
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower index
message object (0 to 13) is updated first.
This flag can generate an interrupt.
4BERR
Bit Error (Only in Transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the arbitration field
and the acknowledge slot detecting a dominant bit during the sending of an
error frame.
This flag can generate an interrupt.
3SERR
Stuff Error
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt.
2CERR
CRC Error
The receiver performs a CRC check on each destuffed received message
from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is
set.
This flag can generate an interrupt.
1FERR
Form Error
The form error results from one or more violations of the fixed form in the
following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt.
0AERR
Acknowledgment Error
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt.