Datasheet

114

AT89C51CC03

4182O–CAN–09/08

Table 60. CANBT1 Register

CANBT1 (S:B4h)

CAN Bit Timing Registers 1

Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 52.

No default value after reset.

76543210

- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -

Bit

Number Bit Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-1 BRP5:0

Baud rate prescaler

The period of the CAN controller system clock Tscl is programmable and

determines the individual bit timing.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tscl =

BRP[5..0] + 1

Fcan