Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 44 (16.59x16.59) 8-Bit 40 MHz I/O number 36

Rev. 4182O–CAN–09/08

Features

• 80C51 Core Architecture

• 256 Bytes of On-chip RAM

• 2048 Bytes of On-chip ERAM

• 64K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Read/Write Cycle: 100K

• 2K Bytes of On-chip Flash for Bootloader

• 2K Bytes of On-chip EEPROM

Read/Write Cycle: 100K

• Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

• 14-sources 4-level Interrupts

• Three 16-bit Timers/Counters

• Full Duplex UART Compatible 80C51

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

• Five Ports: 32 + 4 Digital I/O Lines

• Five-channel 16-bit PCA with

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

• Double Data Pointer

• 21-bit WatchDog Timer (7 Programmable Bits)

• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

• SPI Interface, (PLCC52 and VPFP64 packages only)

• Full CAN Controller

– Fully Compliant with CAN Rev 2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 15 Independent Message Objects

– Each Message Object Programmable on Transmission or Reception

– Individual Tag and Mask Filters up to 29-bit Identifier/Channel

– 8-byte Cyclic Data Register (FIFO)/Message Object

– 16-bit Status and Control Register/Message Object

– 16-bit Time-Stamping Register/Message Object

– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

– Access to Message Object Control and Data Registers Via SFR

– Programmable Reception Buffer Length Up To 15 Message Objects

– Priority Management of Reception of Hits on Several Message Objects at the

Same Time (Basic CAN Feature)

– Priority Management for Transmission

– Message Object Overrun Interrupt

– Supports

– Time Triggered Communication

– Autobaud and Listening Mode

– Programmable Automatic Reply Mode

– 1-Mbit/s Maximum Transfer Rate at 8 MHz

(1)

Crystal Frequency in X2 Mode

– Readable Error Counters

– Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization

– Independent Baud Rate Prescaler

– Data, Remote, Error and Overload Frame Handling

1. At BRP = 1 sampling point will be fixed.

Enhanced 8-bit

MCU with CAN

Controller and

Flash Memory

AT89C51CC03

Summary of content (198 pages)

PAGE 1
Features • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip Flash for Bootloader • 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K • Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply • 14-sources 4-level Interrupts • Three 16-bit Timers/Counters • Full Duplex UART Compatible 80C51 • High-speed Architecture – In Standard Mode: 40 MHz (Vcc
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• On-chip Emulation Logic (Enhanced Hook System) • Power Saving Modes – Idle Mode – Power-down Mode • Power Supply: 3 volts to 5.5 volts • Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C) • Packages: VQFP44, PLCC44, VQFP64, PLCC52 Description The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.
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AT89C51CC03 6 5 4 3 2 1 44 43 42 41 40 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 Pin Configuration 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6/WR P3.7/RD P4.0/ TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.
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3 2 VCC XTAL1 XTAL2 VAGND RESET VSS TESTI VCC 5 4 1 52 51 50 49 48 47 8 46 9 10 45 44 11 43 12 13 42 14 41 PLCC52 ALE PSEN P0.7/AD7 P0.6/AD6 NC P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 15 40 39 16 38 17 37 18 36 19 35 P4.4/MOSI P0.0 /AD0 34 P2.0/A8 21 22 23 24 25 26 27 28 29 30 31 32 33 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P4.2/MISO 20 P3.6/WR P3.7/RD P4.0/TxDC P4.1/RxDC P2.7/A15 P2.6/A14 NC P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/SS 6 VAREF P1.
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AT89C51CC03 Pin Name Type Description VSS GND Circuit ground TESTI I VCC Must be connected to VSS Supply Voltage VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.
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Pin Name Type P3.0:7 I/O Description Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.
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AT89C51CC03 Pin Name Type RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. O ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access.
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Figure 1. Port 1, Port 3 and Port 4 Structure VCC ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL BUS READ PIN Port 0 and Port 2 P1.x P3.x P4.x D P1.X Q P3.X P4.X LATCH CL WRITE TO LATCH Note: INTERNAL PULL-UP (1) ALTERNATE INPUT FUNCTION The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups.
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AT89C51CC03 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2) READ LATCH P2.x (1) 1 INTERNAL BUS WRITE TO LATCH D P2.X LATCH Q 0 READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
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write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero.
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AT89C51CC03 SFR Mapping The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following categories: Mnemonic Add Name 7 6 5 4 3 2 1 0 ACC E0h Accumulator – – – – – – – – B F0h B Register – – – – – – – – PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P SP 81h Stack Pointer – – – – – – – – DPL 82h Data Pointer Low byte – – – – – – – – – – – – – – – – LSB of DPTR DPH 83h Data Pointer High byte MSB of DPTR Mnemonic
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Mnemonic Add Name 7 6 5 4 3 2 1 0 T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# T2MOD C9h Timer/Counter 2 Mode – – – – – – T2OE DCEN RCAP2H Timer/Counter 2 CBh Reload/Capture High byte – – – – – – – – RCAP2L Timer/Counter 2 CAh Reload/Capture Low byte – – – – – – – – WDTRST A6h WatchDog Timer Reset – – – – – – – – WDTPRG A7h WatchDog Timer Program – – – – – S2 S1 S0 Mnemonic Add Name 7 6 5 4 3 2
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AT89C51CC03 Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0 IEN1 E8h Interrupt Enable Control 1 – – – – ESPI ETIM EADC ECAN IPL0 B8h Interrupt Priority Control Low 0 – PPC PT2 PS PT1 PX1 PT0 PX0 IPH0 B7h Interrupt Priority Control High 0 – PPCH PT2H PSH PT1H PX1H PT0H PX0H IPL1 F8h Interrupt Priority Control Low 1 – – – – SPIL POVRL PADCL PCANL IPH1 F7h Interrupt Priority Control High1 –
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Mnemonic Add Name 7 6 5 4 3 2 1 0 CANIE2 C3h CAN Interrupt Enable Channel byte 2 IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0 CANSIT1 BAh CAN Status Interrupt Channel byte1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 CANSIT2 BBh CAN Status Interrupt Channel byte2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 CANTCON A1h CAN Timer Control TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 CANTIMH ADh CAN Timer high CANTIM 15 CANTIM 14
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AT89C51CC03 Mnemonic CANIDT4 CANIDM1 CANIDM2 CANIDM3 CANIDM4 Add Name BFh C4h C5h C6h C7h 7 6 5 4 3 CAN Identifier Tag byte 4(PartA) – – – – – CAN Identifier Tag byte 4(PartB) IDT4 IDT3 IDT2 IDT1 IDT0 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 IDMSK4 IDMSK3 IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 IDMSK2 IDMSK1 IDMSK0 – – – – – IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 – – – – – – – – IDMSK12 I
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Table 1.
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AT89C51CC03 Clock The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency.
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Figure 5. Clock CPU Generation Diagram X2B Hardware byte PCON.0 On RESET IDL X2 CKCON.0 ÷2 XTAL1 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol and ADC PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FCan Clock 0 ÷2 1 FSPIClock 0 X2 PERIPH CLOCK CKCON.0 SPIX2 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON1.0 CKCON0.7 CKCON0.6 CKCON0.5 CKCON0.4 CKCON0.3 CKCON0.2 CKCON0.
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AT89C51CC03 Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: X2 Mode STD Mode In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
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Registers Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register 7 6 5 4 3 2 1 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 CANX2 CAN clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6 WDX2 WatchDog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
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AT89C51CC03 Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register 1 7 6 5 4 3 2 1 0 SPIX2 Bit Number 7-1 0 Note: Bit Mnemonic Description - SPIX2 Reserved The value read from these bits is indeterminate. Do not set these bits. SPI clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.
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Data Memory The AT89C51CC03 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 2048 Bytes RAM segment (ERAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 8 shows the internal and external data memory spaces organization.
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AT89C51CC03 Internal Space Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6) select which bank is in use according to Table 4.
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External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5 describes the external memory interface signals. Figure 10.
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AT89C51CC03 Figure 11. External Data Read Waveforms CPU Clock ALE RD#1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 12. External Data Write Waveforms CPU Clock ALE WR#1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
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Dual Data Pointer Description The AT89C51CC03 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13). Figure 13.
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AT89C51CC03 Registers Table 6. PSW Register PSW (S:8Eh) Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 2 OV Overflow Flag Overflow set by arithmetic operations. 1 F1 User Definable Flag 1 0 P Parity Bit Set when ACC contains an odd number of 1’s.
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Bit Number 4-2 1 0 Bit Mnemonic Description XRS1-0 EXTRAM A0 ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration after reset) 110 Reserved 111 Reserved Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal ERAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access.
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AT89C51CC03 Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51CC03 is powered up.
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Figure 15. Power Fail Detect Vcc t Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.
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AT89C51CC03 Reset Introduction The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 16. Reset Schematic Power Monitor Hardware Watchdog Internal Reset PCA Watchdog RST Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VCC as shown in Figure 17.
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Reset Output As detailed in Section “Watchdog Timer”, page 81, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown Figure 18. Figure 18.
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AT89C51CC03 Power Management Introduction Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Clock”, page 17. Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts.
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Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level. There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt.
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AT89C51CC03 Table 9.
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Registers Table 10. PCON Register PCON (S87:h) Power configuration Register 7 6 5 4 3 2 1 0 - - - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. 7-4 - 3 GF1 General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
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AT89C51CC03 EEPROM Data Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
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Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read.
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AT89C51CC03 Registers Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Program/Code Memory The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage.
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AT89C51CC03 External Code Memory Access Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 21 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21 describes the external memory interface signals. Figure 21.
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Figure 22. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 PCL P2 PCH Flash Memory Architecture D7:0 PCL D7:0 PCH PCH AT89C51CC03 features two on-chip Flash memories: • Flash memory FM0: containing 64K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API).
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AT89C51CC03 Figure 24.
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FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 23): • The memory array (user space) 64K Bytes • The Extra Row • The Hardware security bits • The column latch registers User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain information for boot loader usage.
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AT89C51CC03 Code executing from Cross Flash Memory Access FM0 (user Flash) FM1 (boot Flash) Action FM0 (user Flash) FM1 (boot Flash) Read ok - Load column latch ok - Write - - Read ok ok Load column latch ok - Write ok - Read (a) - External memory Load column latch - - EA = 0 Write - - (a) Depend upon general lock bit configuration.
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Overview of FM0 Operations Flash Registers (SFR) The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. FCON Register Table 13.
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AT89C51CC03 FSTA Register Table 14.
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Table 16. Programming Spaces Write to FCON FPL3:0 FPS FMOD1 FMOD0 Operation 5 X 0 0 No action A X 0 0 Write the column latches in user space 5 X 0 1 No action A X 0 1 Write the column latches in extra row space User Extra Row Hardware Security Byte 5 X 1 0 No action A X 1 0 Write the fuse bits space Reset 5 X 1 1 No action Columns Latches A X 1 1 Reset the column latches Notes: Status of the Flash Memory 1.
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AT89C51CC03 order. The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page Notes: 1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register will be set. 2.
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Figure 25. Column Latches Loading Procedure Column Latches Loading Save and Disable IT EA = 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT Note: The last page address used when loading the column latch is the one used to select the page programming address.
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AT89C51CC03 Figure 26. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 25 Save and Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Clear Mode FCON = 00h End Programming Restore IT Hardware Security Byte The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 27: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and disable the interrupts.
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Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable IT EA = 0 Save and Disable IT EA = 0 FCON = 0Ch Launch Programming FCON = 54h FCON = A4h Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A FBusy Cleared? End Loading Restore IT Clear Mode FCON = 00h End Programming RestoreIT Reset the Column Latches An automatic reset of the column latches is performed after a successful Flash write sequence.
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AT89C51CC03 Power Down Request Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is in progress (check BUSY=0), then check that the column latches are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if necessary. Reading the Flash Spaces User The following procedure is used to read the User space: • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR=read@.
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Table 17. Program Lock Bit Program Lock Bits Security level LB0 LB1 LB2 1 U U U No program lock features enabled. U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. 2 P U Protection Description ISP and software programming with API are still allowed.
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AT89C51CC03 Operation Cross Memory Access Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • XRAM (eXternal RAM) • EEPROM DATA • FM0 ( user flash ) • Hardware byte • XROW • Boot Flash • Flash Column latch The table below provide the different kind of memory which can be accessed from different code location. Table 18.
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Sharing Instructions Table 19. Instructions shared XRAM Action RAM ERAM EEPROM DATA Boot FLASH FM0 Hardware Byte XROW Read MOV MOVX MOVX MOVC MOVC MOVC MOVC Write MOV MOVX MOVX - by cl by cl by cl Note: by cl : using Column Latch Table 20. Read MOVX A, @DPTR Flash EEE bit in FPS in XRAM EECON Register FCON Register ENBOOT EA ERAM 0 0 X X OK 0 1 X X OK 1 0 X X 1 1 X X EEPROM DATA Column Latch OK OK Table 21.
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AT89C51CC03 Table 22.
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In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C51CC03 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before assembly the 1st personalization of the product by programming in the FM0 and if needed also a customized Boot loader in the FM1.
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AT89C51CC03 Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FCh (no user boot loader in FM0). - To read or modify this byte, the APIs are used.
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Figure 30. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 register is initialized with BLJB. RESET Hardware Hardware condition? No ENBOOT = 0 PC = 0000h No ENBOOT = 1 PC = F800h FCON = 00h Yes FCON = F0h BLJB = = 0 ? Yes Software ENBOOT = 1 PC = F800h Application in FM0 Application Programming Interface Boot Loader in FM1 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages.
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AT89C51CC03 Hardware Security Byte Table 24. Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7 X2B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. 6 BLJB Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Reserved The value read from these bits are indeterminate.
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Serial I/O Port The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition Figure 31.
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AT89C51CC03 valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 33. and Figure 34.). Figure 33. UART Timing in Mode 1 RXD D0 D1 D2 Start bit D3 D4 D5 D6 D7 Stop bit Data byte RI SMOD0=X FE SMOD0=1 Figure 34.
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Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
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AT89C51CC03 For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Registers Table 25.
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Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 27. SADDR Register SADDR (S:A9h) Slave Address Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description 7-0 Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 28.
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AT89C51CC03 Table 29. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 – POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage.
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Timers/Counters The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
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AT89C51CC03 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 35). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 35.
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Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 37.
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AT89C51CC03 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 35 to Figure 37 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode. • Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 31) and bits 2, 3, 6 and 7 of TCON register (see Figure 30).
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Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 39. Timer Interrupt System Timer 0 Interrupt Request TF0 TCON.5 ET0 IEN0.1 Timer 1 Interrupt Request TF1 TCON.7 ET1 IEN0.3 Registers Table 30.
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AT89C51CC03 Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
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Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description 7:0 Low Byte of Timer 0. Reset Value = 0000 0000b Table 34.
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AT89C51CC03 Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7:0 Bit Mnemonic Description Low Byte of Timer 1.
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Timer 2 The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
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AT89C51CC03 Programmable ClockOutput In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 41). The input clock increments TL2 at frequency F OSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts.
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Registers Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
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AT89C51CC03 Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 41.
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AT89C51CC03 Watchdog Timer AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) register.
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Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42.
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AT89C51CC03 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is significantly different.
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Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7 Bit Mnemonic Description - Watchdog Control Value Reset Value = 1111 1111b Note: 84 The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences.
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AT89C51CC03 CAN Controller The CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1-Mbit/sec at 8 MHz1 Crystal frequency in X2 mode. Note: 1. At BRP = 1 sampling point will be fixed.
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number of following data bytes in the "Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly.
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AT89C51CC03 Figure 45. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
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Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2.
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AT89C51CC03 fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". Error at Bit Level • ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. • Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals.
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Figure 47. CAN Controller Block Diagram Bit Stuffing /Destuffing TxDC RxDC Bit Timing Logic Error Counter Rec/Tec Cyclic Redundancy Check Receive Page Register DPR(Mailbox + Registers) Transmit Priority Encoder µC-Core Interface Interface Bus CAN Controller Mailbox and Registers Organization 90 Core Control The pagination allows management of the 321 registers including 300(15x20) Bytes of mailbox via 34 SFR’s.
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AT89C51CC03 Figure 48.
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Working on Message Objects The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8.
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AT89C51CC03 Buffer Mode Any message object can be used to define one buffer, including non-consecutive message objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Figure 49.
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IT CAN Management The different interrupts are: • Transmission interrupt, • Reception interrupt, • Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), • Interrupt when Buffer receive is full, • Interrupt on overrun of CAN Timer. Figure 50. CAN Controller Interrupt Structure CANGIE.5 ENRX CANGIE.4 CANGIE.3 ENTX ENERCH RXOK i CANSIT1/2 CANSTCH.5 SIT i TXOK i CANSTCH.6 CANIE1/2 BERR i EICH i CANSTCH.4 i=0 SERR i CANSTCH.3 SIT i CERR i i=14 CANSTCH.
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AT89C51CC03 • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To enable an interrupt on general error: • Enable General CAN IT in the interrupt system register, • Enable interrupt on error, ENERG. To enable an interrupt on Buffer-full condition: • Enable General CAN IT in the interrupt system register, • Enable interrupt on Buffer full, ENBUF.
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Bit Timing and Baud Rate FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field and segment abbreviations: • BRP: Baud Rate Prescaler. • TQ: Time Quantum (output of Baud Rate Prescaler). • SYNS: SYNchronization Segment is 1 TQ long. • PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. • PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
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AT89C51CC03 Figure 52.
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Fault Confinement With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent.
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AT89C51CC03 Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register Figure 54.
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Description of the different steps for: Data Frame message object in transmission 0 1 u u x 0 0 u u u message object disabled 0 0 u c x 1 0 u c u DA TA F RA ME message object in transmission 1 1 u u x 0 0 u u u message object in reception by CAN controller 0 1 c u x 1 0 u c u message object disabled 0 0 u c x 0 1 u u c 1 1 u u x 0 0 u u u message object disabled 0 1 c u x 1 0 u c u 0 0 c c FR AM E ME FRA ) TA diate A D me (im x 0 1 u u c RE MO TE F RA ME ME RA A F red) T DA efer
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AT89C51CC03 Time Trigger Communication (TTC) and Message Stamping The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register.
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CAN Autobaud and Listening Mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 56.
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AT89C51CC03 // Enable the CAN macro CANGCON = 02h 2.
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4.
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AT89C51CC03 CAN SFR’s Table 47.
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Registers Table 48. CANGCON Register CANGCON (S:ABh) CAN General Control Register 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description ABRQ Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control and DLC register) is done for each message object.
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AT89C51CC03 Table 49. CANGSTA Register CANGSTA (S:AAh Read Only) CAN General Status Register 7 6 5 4 3 2 1 0 - OVFG - TBSY RBSY ENFG BOFF ERRP Bit Number 7 Bit Mnemonic Description - Reserved The values read from this bit is indeterminate. Do not set this bit. Overload Frame Flag 6 OVFG 5 - This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit is indeterminate.
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Table 50. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt 7 6 5 4 3 2 1 0 CANIT - OVRTIM OVRBUF SERG CERG FERG AERG Bit Number Bit Mnemonic Description General Interrupt Flag(1) CANIT 6 - 5 OVRTIM Overrun CAN Timer This status bit is set when the CAN timer switches 0xFFFF to 0x0000. If the bit ETIM in the IE1 register is set, an interrupt is generated. Clear this bit in order to reset the interrupt. 4 OVRBUF Overrun BUFFER 0 - no interrupt.
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AT89C51CC03 Table 51. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Bit Number 7-0 Bit Mnemonic Description TEC7:0 Transmit Error Counter see Figure 53 Reset Value = 00h Table 52.
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Table 53. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable 7 6 5 4 3 2 1 0 - - ENRX ENTX ENERCH ENBUF ENERG - Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits.
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AT89C51CC03 Table 54. CANEN1 Register CANEN1 (S:CEh Read Only) CAN Enable Message Object Registers 1 7 6 5 4 3 2 1 0 - ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8 Bit Number Bit Mnemonic Description 7 - Reserved The values read from this bit is indeterminate. Do not set this bit. Enable Message Object 6-0 ENCH14:8 These bits provide the availability of the MOb. It is set to one when the MOb is enabled.
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Table 56. CANSIT1 Register CANSIT1 (S:BAh Read Only) CAN Status Interrupt Message Object Registers 1 7 6 5 4 3 2 1 0 - SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 Bit Number Bit Mnemonic Description 7 - Reserved The values read from this bit is indeterminate. Do not set this bit. Status of Interrupt by Message Object 6-0 SIT14:8 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT14:8 = 0b 0000 1001 -> IT’s on message objects 11 and 8. see Figure 50.
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AT89C51CC03 Table 58. CANIE1 Register CANIE1 (S:C2h) CAN Enable Interrupt Message Object Registers 1 7 6 5 4 3 2 1 0 - IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8 Bit Number Bit Mnemonic Description 7 6-0 - IECH14:8 Reserved The values read from this bit is indeterminate. Do not set this bit. Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH14:8 = 0b 0000 1100 -> Enable IT’s of message objects 11 and 10. see Figure 50. Reset Value = x000 0000b Table 59.
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Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers 1 7 6 5 4 3 2 1 0 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. 6-1 BRP5:0 BRP[5..0] + 1 Tscl = Fcan 0 Note: - Reserved The value read from this bit is indeterminate.
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AT89C51CC03 Table 61. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers 2 7 6 5 4 3 2 1 0 - SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 - Bit Number 7 6-5 Bit Mnemonic Description - SJW1:0 Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission.
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Table 62. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers 3 7 6 5 4 3 2 1 0 - PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width. 6-4 PHS2 2:0 Tphs2 = Tscl x (PHS2[2..
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AT89C51CC03 Table 63. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register 7 6 5 4 3 2 1 0 CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0 Bit Number Bit Mnemonic Description 7-4 CHNB3:0 3 AINC 2-0 INDX2:0 Selection of Message Object Number The available numbers are: 0 to 14 (see Figure 48). Auto Increment of the Index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index.
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Table 65. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Bit Number DLCW Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. TXOK Transmit OK The communication enabled by transmission is completed.
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AT89C51CC03 Table 66. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers 1 7 6 5 4 3 2 1 0 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3 Bit Number 7-0 Bit Mnemonic Description IDT10:3 IDentifier tag value See Figure 54. No default value after reset. Table 67. CANIDT2 Register for V2.0 part A CANIDT2 for V2.
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Table 69. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRTAG - RB0TAG Bit Number Bit Mnemonic Description 7-3 - 2 RTRTAG 1 - 0 RB0TAG Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Tag Value. Reserved The values read from this bit are indeterminate. Do not set these bit. Reserved Bit 0 Tag Value. No default value after reset. Table 70.
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AT89C51CC03 Table 72. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 Bit Number 7-0 Bit Mnemonic Description IDT12:5 IDentifier Tag Value See Figure 54. No default value after reset. Table 73. CANIDT4 Register for V2.0 part B CANIDT4 for V2.
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Table 75. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 2 IDMSK 1 IDMSK 0 - - - - - Bit Number Bit Mnemonic Description 7-5 IDTMSK2:0 4-0 - IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54. Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. Table 76. CANIDM3 Register for V2.0 part A CANIDM3 for V2.
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AT89C51CC03 Table 77. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 - 2 RTRMSK 1 - 0 IDEMSK Note: Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 79. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13 Bit Number 7-0 Note: Bit Mnemonic Description IDMSK20:13 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54. The ID Mask is only used for reception. No default value after reset. Table 80. CANIDM3 Register for V2.0 part B CANIDM3 for V2.
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AT89C51CC03 Table 81. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 IDMSK4:0 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 54. 2 RTRMSK Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled.
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Table 83. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl 7 6 5 4 3 2 1 0 TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 Bit Number 7-0 Bit Mnemonic Description TPRESC7:0 Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 55. Reset Value = 00h Table 84.
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AT89C51CC03 Table 86. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High 7 6 5 4 3 2 TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 Bit Number 7-0 1 0 TIMSTMP 9 TIMSTMP 8 Bit Mnemonic Description TIMSTMP15: High byte of Time Stamp 8 See Figure 55. No default value after reset Table 87.
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Table 89. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low 7 6 5 4 3 2 1 0 TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number 7-0 Bit Mnemonic Description TIMTTC7:0 Low byte of TTC Timer See Figure 55.
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AT89C51CC03 Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
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In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: • The device is configured as a Master and the SSDIS control bit in SPCON is set.
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AT89C51CC03 Functional Description Figure 58 shows a detailed structure of the SPI Module. Figure 58.
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When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 59). Figure 59.
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AT89C51CC03 Figure 60. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 61.
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When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. So it is possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared. Figure 63 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immediately sent on the bus.
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AT89C51CC03 Error Conditions The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault Error (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. • Mode fault detection in Master mode: MODF is set to warn that there may be a multi-master conflict for system control.
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Figure 65. Mode Fault Conditions in Slave Mode 0 SCK cycle # SCK (from master) MOSI (from master) 0 OverRun Condition 2 3 4 MSB B6 B5 B4 1 z 0 1 z 0 MISO (from slave) 1 z 0 SS (slave) 1 z 0 MSB MSB MODF detected Note: 1 B6 MODF detected when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
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AT89C51CC03 Figure 66. SPI Interrupt Requests Generation SPIF SPTEIE SPI CPU Interrupt Request SPTE MODFIE MODF Registers Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs.
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Bit Number Bit Mnemonic 3 CPOL Description Clock Polarity Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock Phase 2 Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). CPHA Set to have the data sampled when the SCK returns to idle state (see CPOL).
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AT89C51CC03 Bit Number Bit Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR 4 MODF When MODF error occurred: - In slave mode: SPI interface ignores all transmitted data while SS remains high. A new transmission is perform as soon as SS returns low. - In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in SPCON register).
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SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: • 140 Do not change SPR2, SPR1 and SPR0 • Do not change CPHA and CPOL • Do not change MSTR • Clearing SPEN would immediately disable the peripheral • Writing to the SPDAT will cause an overflow.
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AT89C51CC03 Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
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Figure 67. PCA Timer/Counter To PCA modules FPca/6 overflow FPca/2 CH T0 OVF It CL 16 bit up counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 Idle CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the WatchDog function on module 4.
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AT89C51CC03 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • The PWM bit enables the pulse width modulation mode.
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Figure 69. PCA Capture Mode PCA Counter CH CL (8bits) (8bits) CEXn n = 0, 4 CCAPnH CCAPnL PCA Interrupt Request CCFn CCON CAPMn ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 0 7 CCAPMn Register (n = 0, 4) 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register.
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AT89C51CC03 High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Figure 71.
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Figure 72. PCA PWM Mode CCAPnH CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL “0” CL < CCAPnL 8-Bit Comparator CL (8 bits) CEX CL > = CCAPnL “1” PCA WatchDog Timer ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with the PCA to improve system reliability without increasing chip count. WatchDog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge.
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AT89C51CC03 PCA Registers Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 7 CIDL 6 WDTE 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 96. CCON Register CCON (S:D8h) PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
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AT89C51CC03 Table 97. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number 7:0 Bit Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 98.
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Table 99. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number 7 Bit Mnemonic Description - Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function.
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AT89C51CC03 Table 100. CH Register CH (S:F9h) PCA Counter Register High Value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7:0 Bit Mnemonic Description CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 101.
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Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51CC03. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two kinds of conversion are available: - Standard conversion (8 bits).
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AT89C51CC03 Figure 73. ADC Description ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 IEN1.1 ADCIN 8 ADDH 2 ADDL + SAR - AVSS Sample and Hold 111 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 74 shows the timing diagram of a complete conversion.
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ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 76). Clear this flag for rearming the interrupt.
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AT89C51CC03 Figure 75. A/D Converter Clock CPU CLOCK ÷2 Prescaler ADCLK ADC Clock A/D CPU Core Clock Symbol Converter ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 µW. IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 76.
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EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: 156 to enable the ADC interrupt: EA = 1 AT89C51CC03 4182O–CAN–09/08
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AT89C51CC03 Registers Table 103. ADCF Register ADCF (S:F6h) ADC Configuration 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7-0 Bit Mnemonic Description CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value =0000 0000b Table 104.
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Table 105. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic Description 7-5 - 4-0 PRS4:0 Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler See Note (1) Reset Value = XXX0 0000b Note: 1. In X1 mode: For PRS > 0 FADC = FXTAL 4xPRS For PRS = 0 FADC = FXTAL 128 In X2 mode: For PRS > 0 FADC = FXTAL 2xPRS For PRS = 0 FADC = FXTAL 64 Table 106.
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AT89C51CC03 Bit Number Bit Mnemonic Description 7-2 - 1-0 ADAT1:0 Reserved The value read from these bits are indeterminate. Do not set these bits.
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Interrupt System Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 77. Interrupt Control System INT0# 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1# External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.
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AT89C51CC03 Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination.
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Registers Table 110. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
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AT89C51CC03 Table 111. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - ESPI ETIM EADC ECAN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 112. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPC PCA Interrupt Priority bit Refer to PPCH for priority level 5 PT2 Timer 2 Overflow Interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial Port Priority bit Refer to PSH for priority level.
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AT89C51CC03 Table 113. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - - - - SPIL POVRL PADCL PCANL Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
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Table 114. IPL0 Register IPH0 (B7h) Interrupt High Priority Register 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C51CC03 Table 115. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1 7 6 5 4 3 2 1 0 - - - - SPIH POVRH PADCH PCANH Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
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Electrical Characteristics Absolute Maximum Ratings Note: Ambiant Temperature Under Bias: I = industrial........................................................-40°C to 85°C A = automotive..................................................-40°C to +125°C Voltage on VCC from VSS ......................................-0.5V to + 6V Voltage on Any Pin from VSS ..................... -0.5V to VCC + 0.2V Power Dissipation ..............................................................
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AT89C51CC03 Table 116. DC Parameters in Standard Voltage (Continued) Symbol VOH Parameter Output High Voltage, ports 1, 2, 3, and 4 VOH1 Output High Voltage, port 0, ALE, PSEN RRST RST Pulldown Resistor Min Typ(5) Max Unit VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V VCC - 0.3 V VCC - 0.7 V VCC - 1.5 V 20 100 200 kΩ Test Conditions IOH = -10 μA IOH = -30 μA IOH = -60 μA VCC = 3V to 5.5V IOH = -200 μA IOH = -3.2 mA IOH = -7.
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Power Fail Detect at Ambiant Temperatures VPFDP(1) VPFDM(2) Hysterisis 2.5V typ 2.35V typ 100mV min. Note: 1. Threshold Voltage for PFD Release 2. Threshold Voltage for PFD Activation Figure 78. ICC Test Condition, Active Mode VCC ICC VCC VCC P0 VCC RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL VSS All other pins are disconnected. Figure 79. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 80.
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AT89C51CC03 Figure 81. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. DC Parameters for A/D Converter 0.7VCC 0.2VCC-0.1 Table 117. DC Parameters for AD Converter in Precision Conversion Symbol Parameter AVin Analog input voltage Rref Resistance between Vref and Vss Vref(3) Reference voltage Cai Analog input Capacitance Rai Analog input Resistor INL Integral non linearity Min Typ(1),(2) Vss- 0.2 12 16 2.40 Max Unit Vref + 0.
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External Program Memory Characteristics Table 118. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 119.
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AT89C51CC03 Table 120. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TLHLL Min 2T-x T-x 10 ns TAVLL Min T-x 0.5 T - x 15 ns TLLAX Min T-x 0.5 T - x 15 ns TLLIV Max 4T-x 2T-x 30 ns TLLPL Min T-x 0.5 T - x 10 ns TPLPH Min 3T-x 1.5 T - x 20 ns TPLIV Max 3T-x 1.5 T - x 40 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 7 ns TAVIV Max 5T-x 2.
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External Data Memory Characteristics Table 121. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Table 122.
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AT89C51CC03 Table 123. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TRLRH Min 6T-x 3T-x 20 ns TWLWH Min 6T-x 3T-x 20 ns TRLDV Max 5T-x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 ns TLLDV Max 8T-x 4T -x 40 ns TAVDV Max 9T-x 4.5 T - x 60 ns TLLWL Min 3T-x 1.5 T - x 25 ns TLLWL Max 3T+x 1.5 T + x 25 ns TAVWL Min 4T-x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.
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External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TQVWX TLLAX PORT 0 A0-A7 TWHQX TQVWH DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TAVWL PORT 2 TRHDX A0-A7 ADDRESS OR SFR-P2 DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 Serial Port Timing – Shift Register Mode Table 124.
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AT89C51CC03 Table 125. AC Parameters for a Fix Clock (F = 40 MHz) Symbol Min Max TXLXL 300 ns TQVHX 200 ns TXHQX 30 ns TXHDX 0 ns TXHDV Units 117 ns Table 126.
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External Clock Drive Waveforms VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCX TCLCH TCLCX TCHCL TCLCL AC Testing Input/Output Waveforms VCC -0.5V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.
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AT89C51CC03 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
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Flash/EEPROM Memory Table 128. Timing Symbol Definitions Signals Conditions S (Hardware condition) PSEN#,EA L Low R RST V Valid B FBUSY flag X No Longer Valid Table 129. Memory AC Timing VDD = 3V to 5.
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AT89C51CC03 Timings Test conditions: capacitive load on all pins= 60 pF. Table 1. SPI Interface Master AC Timing VDD = 2.7 to 3.
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Waveforms Figure 84. SPI Slave Waveforms (SSCPHA= 0) SS (input) TSLCH TSLCL TCHCH SCK (SSCPOL= 0) (input) TCHCX TCLCH TSHSL TCLCX TCHCL SCK (SSCPOL= 1) (input) TCLOX TCHOX TCLOV TCHOV TSLOV MISO (output) TCLSH TCHSH SLAVE MSB OUT BIT 6 TSHOX SLAVE LSB OUT (1) TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 85.
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AT89C51CC03 Figure 86. SPI Master Waveforms (SSCPHA= 0) SS (output) TCHCH SCK (SSCPOL= 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV MISO (output) Port Data Note: MSB OUT TCHOX BIT 6 LSB OUT Port Data 1. SS handled by software using general purpose port pin. Figure 87.
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Ordering Information Table 131.
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AT89C51CC03 Package Drawings VQFP44 185 4182O–CAN–09/08
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STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
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AT89C51CC03 PLCC44 187 4182O–CAN–09/08
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STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
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AT89C51CC03 VQFP64 189 4182O–CAN–09/08
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STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
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AT89C51CC03 PLCC52 191 4182O–CAN–09/08
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Datasheet Change Log Changes from 4182B 09/03 to 4182C 12/03 1. Added Icc Idle, IPD, and Rrst value in “DC Parameters for A/D Converter” on page 171. Changes from 4182C 12/03 to 4182D 01/04 1. Updated SFR Table. – SFR : SPSTR changed to SPSCR – CANSTMH changed to CANSTMPH p15 – CANSTML changed to CANSTMPL p15 – CANCONC changed to CANCONCH p15 2. AC/DC - p.160 IccOP and ICCIdle formulas changed 3. Changed maximum frequency to 60MHz in internal code execution.
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AT89C51CC03 Changes from 4182N 03/08 to 4182O 09/08 1. Correction to SPDT register address Table 94 on page 139.
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Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................... 2 Pin Configuration ................................................................................. 3 I/O Configurations.......................................................
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AT89C51CC03 Registers............................................................................................................. 39 Program/Code Memory ...................................................................... 40 External Code Memory Access .......................................................................... 41 Flash Memory Architecture................................................................................. 42 Overview of FM0 Operations ........................................
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IT CAN Management .......................................................................................... 94 Bit Timing and Baud Rate ................................................................................... 96 Fault Confinement .............................................................................................. 98 Acceptance Filter ................................................................................................ 99 Data and Remote Frame ................................
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AT89C51CC03 DC Parameters for A/D Converter .................................................................... 171 AC Parameters .................................................................................................171 Timings ............................................................................................................. 181 Ordering Information ........................................................................ 184 Package Drawings ..........................................
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.