Datasheet

46
A/T89C51CC01
4129N–CAN–03/08
Table 32. Read MOVC A, @DPTR
Code Execution
FCON Register
ENBOOT DPTR FM1 FM0 XROW
Hardware
Byte
External
CodeFMOD1 FMOD0 FPS
From FM0
0 0 X
0 0000h to 7FFFh OK
1
0000h to 7FFFh OK
F800h to FFFFh Do not use this configuration
0 1 X X
0000 to 007Fh
See
(1)
OK
1 0 X X X OK
1 1 X
0 000h to 7FFFh OK
1
0000h to 7FFFh OK
F800h to FFFFh Do not use this configuration
From FM1
(ENBOOT =1
0 0
0
1
0000h to 7FFF OK
F800h to FFFFh OK
0 X NA
1
1 X OK
0 X NA
0 1 X
1
0000h to 007h
See
(2)
OK
0 NA
1 0 X
1
X
OK
0 NA
1 1 X
1
000h to 7FFFh
OK
0 NA
External code:
EA=0 or Code
Roll Over
X 0 X X X OK
1. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh
2. For DPTR higher than 007Fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to
007Fh