Datasheet

42
A/T89C51CC01
4129N–CAN–03/08
Figure 24. Reading Procedure
Note: 1. aa = 10 for the Hardware Security Byte.
Flash Protection from Parallel
Programming
The three lock bits in Hardware Security Byte (see "In-System-Programming" section)
are programmed according to Table 27 provide different level of protection for the on-
chip code and data located in FM0 and FM1.
The only way to write these bits are the parallel mode. They are set by default to level 4
Table 27. Program Lock bit
Program Lock bits
U: unprogrammed
P: programmed
WARNING: Security level 2 and 3 should only be programmed after Flash and Core
verification.
Preventing Flash Corruption See the “Power Management” section.
Flash Spaces Reading
Flash Spaces Mapping
FCON = 0000aa0b
(1)
Data Read
DPTR = Address
ACC = 0
Exec: MOVC A, @A+DPTR
Clear Mode
FCON = 00h
Program Lock Bits
Protection Description
Security
Level
LB0 LB1 LB2
1 U U U
No program lock features enabled. MOVC instruction executed from
external program memory returns non coded data.
2 P U U
MOVC instructions executed from external program memory are barred
to return code bytes from internal memory, EA is sampled and latched
on reset, and further parallel programming of the Flash is disabled.
3 U P U
Same as 2, also verify through parallel programming interface is
disabled.
4 U U P
Same as 3, also external execution is disabled if code roll over beyond
7FFFh