Datasheet

A/T89C51CC01

4129N–CAN–03/08

Figure 9. Power-down Exit Waveform Using INT1:0#

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the T89C51CC01 and vectors

the CPU to address 0000h.

Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

Table 14. Pin Conditions in Special Operating Modes

INT1:0#

OSC

Power-down phase Oscillator restart phase Active phaseActive phase

Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PSEN#

Reset Floating High High High High High High

Idle

(internal

code)

Data Data Data Data Data High High

Idle

(external

code)

Floating Data Data Data Data High High

Power-

Down(inter

nal code)

Data Data Data Data Data Low Low

Power-

Down

(external

code)

Floating Data Data Data Data Low Low