Datasheet

141
A/T89C51CC01
4129N–CAN–03/08
Table 118. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value = XXXX X000b
bit addressable
7 6 5 4 3 2 1 0
- - - - POVRL PADCL PCANL
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 POVRL
Timer Overrun Interrupt Priority Level Less Significant Bit
Refer to PI2CH for priority level.
1 PADCL
ADC Interrupt Priority Level Less Significant Bit
Refer to PSPIH for priority level.
0 PCANL
CAN Interrupt Priority Level Less Significant Bit
Refer to PKBH for priority level.