Datasheet

135
A/T89C51CC01
4129N–CAN–03/08
Table 110. ADCLK Register
ADCLK (S:F2h)
ADC Clock Prescaler
Reset Value = XXX0 0000b
Table 111. ADDH Register
ADDH (S:F5h Read Only)
ADC Data High Byte Register
Reset Value = 00h
Table 112. ADDL Register
ADDL (S:F4h Read Only)
ADC Data Low Byte Register
Reset Value = 00h
7 6 5 4 3 2 1 0
- - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0
Bit
Number
Bit
Mnemonic Description
7-5 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
4-0 PRS4:0
Clock Prescaler
f
ADC
= fcpu clock/ (4 (or 2 in X2 mode)* PRS )
7 6 5 4 3 2 1 0
ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2
Bit
Number
Bit
Mnemonic Description
7-0 ADAT9:2
ADC result
bits 9-2
7 6 5 4 3 2 1 0
- - - - - - ADAT 1 ADAT 0
Bit
Number
Bit
Mnemonic Description
7-2 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
1-0 ADAT1:0
ADC result
bits 1-0