Datasheet

10
A/T89C51CC01
4129N–CAN–03/08
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 6. PCA SFRs (Continued)
Mnemonic
Add Name 7 6 5 4 3 2 1 0
Table 7. Interrupt SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
IEN0 A8h
Interrupt Enable
Control 0
EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 E8h
Interrupt Enable
Control 1
– – – – – ETIM EADC ECAN
IPL0 B8h
Interrupt Priority
Control Low 0
– PPC PT2 PS PT1 PX1 PT0 PX0
IPH0 B7h
Interrupt Priority
Control High 0
– PPCH PT2H PSH PT1H PX1H PT0H PX0H
IPL1 F8h
Interrupt Priority
Control Low 1
– – – – – POVRL PADCL PCANL
IPH1 F7h
Interrupt Priority
Control High1
– – – – – POVRH PADCH PCANH
Table 8. ADC SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
ADCON F3h ADC Control – PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0
ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
ADCLK F2h ADC Clock – – – PRS4 PRS3 PRS2 PRS1 PRS0
ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2
ADDL F4h ADC Data Low byte – – – – – – ADAT1 ADAT0
Table 9. CAN SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
CANGCON ABh
CAN General
Control
ABRQ OVRQ TTC SYNCTTC
AUT–
BAUD
TEST ENA GRES
CANGSTA AAh
CAN General
Status
– OVFG – TBSY RBSY ENFG BOFF ERRP
CANGIT 9Bh
CAN General
Interrupt
CANIT – OVRTIM OVRBUF SERG CERG FERG AERG
CANBT1 B4h CAN Bit Timing 1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 –
CANBT2 B5h CAN Bit Timing 2 – SJW1 SJW0 – PRS2 PRS1 PRS0 –
CANBT3 B6h CAN Bit Timing 3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP