Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFP 44 (10x10) 8-Bit 40 MHz I/O number 34

Rev. 4129N–CAN–03/08

Features

•

80C51 Core Architecture

•

256 Bytes of On-chip RAM

•

1K Bytes of On-chip XRAM

•

32K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

Erase/Write Cycle: 100K

•

Boot Code Section with Independent Lock Bits

•

2K Bytes of On-chip Flash for Bootloader

•

In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability

•

2K Bytes of On-chip EEPROM

Erase/Write Cycle: 100K

•

14-sources 4-level Interrupts

•

Three 16-bit Timers/Counters

•

Full Duplex UART Compatible 80C51

•

Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)

•

Five Ports: 32 + 2 Digital I/O Lines

•

Five-channel 16-bit PCA with:

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

•

Double Data Pointer

•

21-bit Watchdog Timer (7 Programmable Bits)

•

A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

•

Full CAN Controller:

– Fully Compliant with CAN Rev2.0A and 2.0B

– Optimized Structure for Communication Management (Via SFR)

– 15 Independent Message Objects:

Each Message Object Programmable on Transmission or Reception

Individual Tag and Mask Filters up to 29-bit Identifier/Channel

8-byte Cyclic Data Register (FIFO)/Message Object

16-bit Status and Control Register/Message Object

16-bit Time-Stamping Register/Message Object

CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message

Object

Access to Message Object Control and Data Registers Via SFR

Programmable Reception Buffer Length Up To 15 Message Objects

Priority Management of Reception of Hits on Several Message Objects at the

Same Time (Basic CAN Feature)

Priority Management for Transmission

Message Object Overrun Interrupt

– Supports:

Time Triggered Communication

Autobaud and Listening Mode

Programmable Automatic Reply Mode

– 1-Mbit/s Maximum Transfer Rate at 8 MHz

(1)

Crystal Frequency in X2 Mode

– Readable Error Counters

– Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization

– Independent Baud Rate Prescaler

– Data, Remote, Error and Overload Frame Handling

•

On-chip Emulation Logic (Enhanced Hook System)

•

Power Saving Modes:

– Idle Mode

– Power-down Mode

1. At BRP = 1 sampling point will be fixed.

Enhanced 8-bit

Microcontroller

with CAN

Controller and

Flash Memory

T89C51CC01

AT89C51CC01

Summary of content (167 pages)

PAGE 1
Features • • • • • • • • • • • • • • • • • • • • 1.
PAGE 2
• Power Supply: 3V to 5.5V • Temperature Range: Industrial (-40° to +85°C) • Packages: VQFP44, PLCC44 Description The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC01 provides 32K Bytes of Flash memory including In-System-Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 1.2-Kbyte RAM.
PAGE 3
A/T89C51CC01 6 5 4 3 2 1 44 43 42 41 40 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 Pin Configuration 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6/WR P3.7/RD P4.0/ TxDC P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.
PAGE 4
I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal.
PAGE 5
A/T89C51CC01 Figure 2. Port 0 Structure ADDRESS LOW/ CONTROL DATA VDD (2) READ LATCH P0.x (1) 1 INTERNAL BUS WRITE TO LATCH D P0.X LATCH Q 0 READ PIN Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 3.
PAGE 6
Table 1. Read-Modify-Write Instructions Instruction Description Example ANL logical AND ANL P1, A ORL logical OR ORL P2, A XRL logical EX-OR XRL P3, A JBC jump if bit = 1 and clear bit JBC P1.1, LABEL CPL complement bit CPL P3.0 INC increment INC P2 DEC decrement DEC P2 DJNZ decrement and jump if not zero DJNZ P3, LABEL MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C CLR Px.y clear bit y of Port x CLR P2.4 SET Px.y set bit y of Port x SET P3.
PAGE 7
A/T89C51CC01 Figure 4. Internal Pull-Up Configurations 2 Osc. PERIODS VCC VCC VCC p1(1) p2 p3 P1.x P2.x P3.x P4.x OUTPUT DATA n INPUT DATA READ PIN Note: Port 2 p1 assists the logic-one output for memory bus cycles.
PAGE 8
SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the following categories: Table 2.
PAGE 9
A/T89C51CC01 Table 4.
PAGE 10
Table 6.
PAGE 11
A/T89C51CC01 Table 9.
PAGE 12
Table 9.
PAGE 13
A/T89C51CC01 Table 10. Other SFRs Mnemonic Add Name FCON D1h Flash Control EECON D2h EEPROM Contol 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY EEPL3 EEPL2 EEPL1 EEPL0 – – EEE EEBUSY Table 11.
PAGE 14
Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency.
PAGE 15
A/T89C51CC01 Figure 5. Clock CPU Generation Diagram X2B Hardware byte PCON.0 On RESET IDL X2 CKCON.0 XTAL1 ÷2 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol and ADC PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FCan Clock 0 PERIPH CLOCK X2 CKCON.0 Peripheral Clock Symbol CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.
PAGE 16
Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: 16 X2 Mode STD Mode In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
PAGE 17
A/T89C51CC01 Register Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register 7 6 5 4 3 2 1 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 CANX2 CAN clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6 WDX2 Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
PAGE 18
Power Management Two power reduction modes are implemented in the T89C51CC01: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 Mode detailed in Section “Clock”. Reset Pin In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a high level has to be applied on the RST pin.
PAGE 19
A/T89C51CC01 Warm Reset To achieve a valid reset, the reset signal must be maintained for at least 2 machine cycles (24 oscillator clock periods) while the oscillator is running. The number of clock periods is mode independent (X2 or X1). Watchdog Reset As detailed in Section “PCA Watchdog Timer”, page 123, the WDT generates a 96-clock period pulse on the RST pin.
PAGE 20
of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode. The general-purpose flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt occurred during normal operation or during Idle mode. When Idle mode is exited by an interrupt, the interrupt service routine may examine GF1 and GF0. 2. Generate a reset.
PAGE 21
A/T89C51CC01 Figure 9. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase Power-down phase Oscillator restart phase Active phase 2. Generate a reset. – Notes: A logic high on the RST pin clears PD bit in PCON register directly and asynchronously. This starts the oscillator and restores the clock to the CPU and peripherals.
PAGE 22
Registers Table 15. PCON Register PCON (S:87h) – Power configuration Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when Vcc rises from 0 to its nominal voltage.
PAGE 23
A/T89C51CC01 Data Memory The T89C51CC01 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 1024 Bytes RAM segment (XRAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
PAGE 24
Internal Space Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 11) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 18) select which bank is in use according to Table 16.
PAGE 25
A/T89C51CC01 External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD, WR, and ALE). Figure 13 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17 describes the external memory interface signals. Figure 13.
PAGE 26
Figure 14. External Data Read Waveforms CPU Clock ALE RD 1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. RD signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 15. External Data Write Waveforms CPU Clock ALE WR1 P0 P2 Notes: 26 DPL or Ri P2 D7:0 DPH or P22 1. WR signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
PAGE 27
A/T89C51CC01 Dual Data Pointer Description The T89C51CC01 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 20) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 16). Figure 16.
PAGE 28
Registers Table 18. PSW Register PSW (S:D0h) Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 Register Bank Select Bits Refer to Table 16 for bits description. 2 OV Overflow Flag Overflow set by arithmetic operations.
PAGE 29
A/T89C51CC01 Bit Number 1 Bit Mnemonic Description EXTRAM 0 A0 Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal XRAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access. Disable/Enable ALE) 0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction. Reset Value = X00X 1100b Not bit addressable Table 20.
PAGE 30
EEPROM Data Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 Bytes (the page size).
PAGE 31
A/T89C51CC01 Examples ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read.
PAGE 32
Registers Table 21. EECON Register EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 33
A/T89C51CC01 Program/Code Memory The T89C51CC01 implement 32K Bytes of on-chip program/code memory. Figure 17 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage.
PAGE 34
17.22 External Code Memory Access Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 18 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 18 describes the external memory interface signals. Figure 18.
PAGE 35
A/T89C51CC01 Figure 19. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 PCL P2 PCH Flash Memory Architecture D7:0 PCH PCL D7:0 PCH T89C51CC01 features two on-chip Flash memories: • Flash memory FM0: containing 32K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API).
PAGE 36
FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 20): • The memory array (user space) 32K Bytes • The Extra Row • The Hardware security bits • The column latch registers User Space This space is composed of a 32K Bytes Flash memory organized in 256 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain information for boot loader usage.
PAGE 37
A/T89C51CC01 Overview of FM0 Operations The CPU interfaces to the Flash memory through the FCON register and AUXR1 register. These registers are used to: • Map the memory spaces in the adressable space • Launch the programming of the memory spaces • Get the status of the Flash memory (busy/not busy) Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register.
PAGE 38
Table 26. Programming Spaces Write to FCON User Extra Row Hardware Security Byte Reserved Notes: Status of the Flash Memory FPL3:0 FPS FMOD1 FMOD0 Operation 5 X 0 0 No action A X 0 0 Write the column latches in user space 5 X 0 1 No action A X 0 1 Write the column latches in extra row space 5 X 1 0 No action A X 1 0 Write the fuse bits space 5 X 1 1 No action A X 1 1 No action 1.
PAGE 39
A/T89C51CC01 Figure 21. Column Latches Loading Procedure Column Latches Loading Save and Disable IT EA = 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT Note: The last page address used when loading the column latch is the one used to select the page programming address.
PAGE 40
Figure 22. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 21 Save and Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Clear Mode FCON = 00h End Programming Restore IT Hardware Security Byte 40 The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 23: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and disable the interrupts. • Load DPTR at address 0000h.
PAGE 41
A/T89C51CC01 Figure 23.
PAGE 42
Figure 24. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 0000aa0b(1) Data Read DPTR = Address ACC = 0 Exec: MOVC A, @A+DPTR Clear Mode FCON = 00h Note: Flash Protection from Parallel Programming 1. aa = 10 for the Hardware Security Byte. The three lock bits in Hardware Security Byte (see "In-System-Programming" section) are programmed according to Table 27 provide different level of protection for the onchip code and data located in FM0 and FM1.
PAGE 43
A/T89C51CC01 Registers FCON RegisterFCON (S:D1h) Flash Control Register 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic Description 7-4 FPL3:0 3 FPS 2-1 FMOD1:0 0 FBUSY Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0 (see Table 26) Flash Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. Flash Mode See Table 25 or Table 26.
PAGE 44
Operation Cross Memory Access Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • XRAM (eXternal RAM) • EEPROM DATA • FM0 (user flash) • Hardware byte • XROW • Boot Flash • Flash Column latch The table below provide the different kind of memory which can be accessed from different code location. Table 28.
PAGE 45
A/T89C51CC01 Sharing Instructions Table 29. Instructions shared XRAM Action RAM ERAM EEPROM DATA Boot FLASH FM0 Hardware Byte XROW Read MOV MOVX MOVX MOVC MOVC MOVC MOVC Write MOV MOVX MOVX - by cl by cl by cl Note: by cl: using Column Latch Table 30. Read MOVX A, @DPTR Flash EEE bit in FPS in XRAM EECON Register FCON Register ENBOOT EA ERAM 0 0 X X OK 0 1 X X OK 1 0 X X 1 1 X X EEPROM DATA Column Latch OK OK Table 31.
PAGE 46
Table 32.
PAGE 47
A/T89C51CC01 In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51CC01 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before mounting the chip on the PCB, FM0 Flash can be programmed with the application code.
PAGE 48
Boot Process Software Boot Process Example Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory programming. - To read or modify this bit, the APIs are used.
PAGE 49
A/T89C51CC01 Figure 26. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 register is initialized with BLJB inverted.
PAGE 50
Hardware Security Byte Table 34. Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7 X2B X2 Bit Set this bit to start in standard mode. Clear this bit to start in X2 mode. 6 BLJB Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Reserved The value read from these bits are indeterminate.
PAGE 51
A/T89C51CC01 Serial I/O Port The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3).
PAGE 52
Figure 29. UART Timing in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 Data byte Start bit Stop bit RI SMOD0=X FE SMOD0=1 Figure 30. UART Timing in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
PAGE 53
A/T89C51CC01 Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
PAGE 54
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Registers Table 35.
PAGE 55
A/T89C51CC01 Table 36. SADEN Register SADEN (S:B9h) Slave Address Mask Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Mask Data for Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 37. SADDR Register SADDR (S:A9h) Slave Address Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 38.
PAGE 56
Table 39. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 – POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage.
PAGE 57
A/T89C51CC01 Timers/Counters The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
PAGE 58
Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 31). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 31.
PAGE 59
A/T89C51CC01 Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 33). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 33.
PAGE 60
Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 31 to Figure 33 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode. • Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 41) and bits 2, 3, 6 and 7 of TCON register (see Figure 40).
PAGE 61
A/T89C51CC01 Figure 35. Timer Interrupt System Timer 0 Interrupt Request TF0 TCON.5 ET0 IEN0.1 Timer 1 Interrupt Request TF1 TCON.7 ET1 IEN0.
PAGE 62
Registers Table 40. TCON Register TCON (S:88h) Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
PAGE 63
A/T89C51CC01 Table 41. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
PAGE 64
Table 42. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description High Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 43. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Low Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 44.
PAGE 65
A/T89C51CC01 Table 45. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7:0 Bit Mnemonic Description Low Byte of Timer 1.
PAGE 66
Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 48). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
PAGE 67
A/T89C51CC01 Programmable ClockOutput In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 37). The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts.
PAGE 68
Registers Table 46. T2CON Register T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
PAGE 69
A/T89C51CC01 Table 47. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 70
Table 49. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 50. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 51.
PAGE 71
A/T89C51CC01 Watchdog Timer T89C51CC01 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) register.
PAGE 72
Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 52.
PAGE 73
A/T89C51CC01 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is significantly different.
PAGE 74
Table 55. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7 Bit Mnemonic Description - Watchdog Control Value Reset Value = 1111 1111b Note: 74 The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences.
PAGE 75
A/T89C51CC01 CAN Controller The CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A and 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1-Mbit/sec. at 8 MHz1 Crystal frequency in X2 mode. Note: 1. At BRP = 1 sampling point will be fixed.
PAGE 76
number of following data bytes in the "Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly.
PAGE 77
A/T89C51CC01 Figure 41. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments (producer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 propagation delay Segments (consumer) SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 Sample Point Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output.
PAGE 78
Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resynchronization Jump Width. This segment may not be longer than Phase Segment 2.
PAGE 79
A/T89C51CC01 Error at Bit Level • ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. • Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received.
PAGE 80
Figure 43. CAN Controller Block Diagram Bit Stuffing /Destuffing TxDC RxDC Bit Timing Logic Error Counter Rec/Tec Cyclic Redundancy Check Receive Page Register DPR(Mailbox + Registers) Transmit Priority Encoder µC-Core Interface Interface Bus CAN Controller Mailbox and Registers Organization 80 Core Control The pagination allows management of the 321 registers including 300(15x20) Bytes of mailbox via 34 SFR’s.
PAGE 81
A/T89C51CC01 Figure 44.
PAGE 82
Working on Message Objects The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8.
PAGE 83
A/T89C51CC01 Buffer Mode Any message object can be used to define one buffer, including non-consecutive message objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Figure 45.
PAGE 84
IT CAN Management The different interrupts are: • Transmission interrupt, • Reception interrupt, • Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error), • Interrupt when Buffer receive is full, • Interrupt on overrun of CAN Timer. Figure 46. CAN Controller Interrupt Structure CANGIE.5 ENRX CANGIE.4 CANGIE.3 ENTX ENERCH RXOK i CANSIT1/2 CANSTCH.5 SIT i TXOK i CANSTCH.6 CANIE1/2 BERR i EICH i CANSTCH.4 i=0 SERR i CANGIT.7 CANIT CANSTCH.
PAGE 85
A/T89C51CC01 • Enable reception interrupt, ENRX. To enable an interrupt on message object error: • Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To enable an interrupt on general error: • Enable General CAN IT in the interrupt system register, • Enable interrupt on error, ENERG.
PAGE 86
Bit Timing and Baud Rate FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field and segment abbreviations: • BRP: Baud Rate Prescaler. • TQ: Time Quantum (output of Baud Rate Prescaler). • SYNS: SYNchronization Segment is 1 TQ long. • PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. • PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long.
PAGE 87
A/T89C51CC01 Figure 48.
PAGE 88
Fault Confinement With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent.
PAGE 89
A/T89C51CC01 Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register Figure 50.
PAGE 90
Description of the different steps for: Data Frame Node B RT R EN CH RP L TX V RXOK O K RT R EN CH RP L TX V O RX K O K Node A message object in transmission 0 1 u u x 0 0 u u u message object disabled 0 0 u c x 1 0 u c u RA M E message object in transmission 1 1 u u x 0 0 u u u message object in by CAN controller reception 0 1 c u x 1 0 u c u message object disabled 0 0 u c x 0 1 u u c FR AM E ME FRA ) TA diate A D me (im 1 1 u u x 0 0 u u u message object disabled 0 1 c u x 1 0
PAGE 91
A/T89C51CC01 Time Trigger Communication (TTC) and Message Stamping The T89C51CC01 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register.
PAGE 92
CAN Autobaud and Listening Mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 52.
PAGE 93
A/T89C51CC01 // Enable the CAN macro CANGCON = 02h 2.
PAGE 94
4.
PAGE 95
A/T89C51CC01 CAN SFR’s Table 57.
PAGE 96
Registers Table 58. CANGCON Register CANGCON (S:ABh) CAN General Control Register 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description ABRQ Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control and DLC register) is done for each message object.
PAGE 97
A/T89C51CC01 Table 59. CANGSTA Register CANGSTA (S:AAh Read Only) CAN General Status Register 7 6 5 4 3 2 1 0 - OVFG - TBSY RBSY ENFG BOFF ERRP Bit Number 7 Bit Mnemonic Description - 6 OVFG 5 - Reserved The values read from this bit is indeterminate. Do not set this bit. Overload Frame Flag This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit is indeterminate.
PAGE 98
Table 60. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt 7 6 5 4 3 2 1 0 CANIT - OVRTIM OVRBUF SERG CERG FERG AERG Bit Number 7 CANIT 6 - General Interrupt Flag(1) This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method. Reserved The values read from this bit is indeterminate. Do not set this bit.
PAGE 99
A/T89C51CC01 Table 61. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Bit Number 7-0 Bit Mnemonic Description TEC7:0 Transmit Error Counter see Figure 49 Reset Value = 00h Table 62.
PAGE 100
Table 63. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable 7 6 5 4 3 2 1 0 - - ENRX ENTX ENERCH ENBUF ENERG - Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits.
PAGE 101
A/T89C51CC01 Table 65. CANEN2 Register CANEN2 (S:CFh Read Only) CAN Enable Message Object Registers 2 7 6 5 4 3 2 1 0 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0 Bit Number 7-0 Bit Mnemonic Description ENCH7:0 Enable Message Object 0 - message object is disabled => the message object is free for a new emission or reception. 1 - message object is enabled. This bit is resetable by re-writing the CANCONCH of the corresponding message object. Reset Value = 0000 0000b Table 66.
PAGE 102
Table 67. CANSIT2 Register CANSIT2 (S:BBh Read Only) CAN Status Interrupt Message Object Registers 2 7 6 5 4 3 2 1 0 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 Bit Number 7-0 Bit Mnemonic Description SIT7:0 Status of Interrupt by Message Object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT7:0 = 0b 0000 1001 -> IT’s on message objects 3 and 0 see Figure 46. Reset Value = 0000 0000b Table 68.
PAGE 103
A/T89C51CC01 Table 69. CANIE2 Register CANIE2 (S:C3h) CAN Enable Interrupt Message Object Registers 2 7 6 5 4 3 2 1 0 IECH 7 IECH 6 IECH 5 IECH 4 IECH 3 IECH 2 IECH 1 IECH 0 Bit Number 7-0 Bit Mnemonic Description IECH7:0 Enable interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 and 2. Reset Value = 0000 0000b Table 70.
PAGE 104
Table 71. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers 2 7 6 5 4 3 2 1 0 - SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 - Bit Number 7 6-5 Bit Mnemonic Description - SJW1:0 Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission.
PAGE 105
A/T89C51CC01 Table 72. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers 3 7 6 5 4 3 2 1 0 - PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP Bit Number 7 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit. Phase Segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width. 6-4 PHS2 2:0 Tphs2 = Tscl x (PHS2[2..
PAGE 106
Table 73. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register 7 6 5 4 3 2 1 0 CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0 Bit Number Bit Mnemonic Description 7-4 CHNB3:0 3 AINC 2-0 INDX2:0 Selection of Message Object Number The available numbers are: 0 to 14 (see Figure 44). Auto Increment of the Index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index.
PAGE 107
A/T89C51CC01 Table 75. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR Bit Number Bit Mnemonic Description DLCW Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCONCH register is updated by the received DLC. TXOK Transmit OK The communication enabled by transmission is completed.
PAGE 108
Table 76. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers 1 7 6 5 4 3 2 1 0 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3 Bit Number 7-0 Bit Mnemonic Description IDT10:3 IDentifier tag value See Figure 50. No default value after reset. Table 77. CANIDT2 Register for V2.0 part A CANIDT2 for V2.
PAGE 109
A/T89C51CC01 Table 79. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRTAG - RB0TAG Bit Number Bit Mnemonic Description 7-3 - 2 RTRTAG 1 - 0 RB0TAG Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Tag Value. Reserved The values read from this bit are indeterminate. Do not set these bit. Reserved Bit 0 Tag Value. No default value after reset.
PAGE 110
Table 82. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 Bit Number 7-0 Bit Mnemonic Description IDT12:5 IDentifier Tag Value See Figure 50. No default value after reset. Table 83. CANIDT4 Register for V2.0 part B CANIDT4 for V2.
PAGE 111
A/T89C51CC01 Table 85. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 2 IDMSK 1 IDMSK 0 - - - - - Bit Number Bit Mnemonic Description 7-5 IDTMSK2:0 4-0 - IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. Table 86. CANIDM3 Register for V2.
PAGE 112
Table 87. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 - 2 RTRMSK 1 - 0 IDEMSK Note: Reserved The values read from these bits are indeterminate. Do not set these bits. Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 113
A/T89C51CC01 Table 89. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13 Bit Number 7-0 Note: Bit Mnemonic Description IDMSK20:13 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. The ID Mask is only used for reception. No default value after reset. Table 90. CANIDM3 Register for V2.0 part B CANIDM3 for V2.
PAGE 114
Table 91. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK Bit Number Bit Mnemonic Description 7-3 IDMSK4:0 IDentifier Mask Value 0 - comparison true forced. 1 - bit comparison enabled. See Figure 50. 2 RTRMSK Remote Transmission Request Mask Value 0 - comparison true forced. 1 - bit comparison enabled.
PAGE 115
A/T89C51CC01 Table 93. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl 7 6 5 4 3 2 1 0 TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 Bit Number 7-0 Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main timer upper counter range = 0 to 255. See Figure 51. TPRESC7:0 Reset Value = 00h Table 94.
PAGE 116
Table 96. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High 7 6 5 4 3 2 TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 Bit Number Bit Mnemonic Description 7-0 TIMSTMP15:8 High byte of Time Stamp See Figure 51. 1 0 TIMSTMP 9 TIMSTMP 8 No default value after reset Table 97.
PAGE 117
A/T89C51CC01 Table 99. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low 7 6 5 4 3 2 1 0 TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number 7-0 Bit Mnemonic Description TIMTTC7:0 Low byte of TTC Timer See Figure 51.
PAGE 118
Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
PAGE 119
A/T89C51CC01 Figure 53. PCA Timer/Counter To PCA modules FPca/6 overflow FPca/2 CH T0 OVF It CL 16 bit up counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 Idle CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the Watchdog function on module 4.
PAGE 120
Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • The PWM bit enables the pulse width modulation mode.
PAGE 121
A/T89C51CC01 Figure 55. PCA Capture Mode PCA Counter CH CL (8bits) (8bits) CEXn n = 0, 4 CCAPnH CCAPnL PCA Interrupt Request CCFn CCON - 0CAPPn CAPNn 000 ECCFn 0 7 CCAPMn Register (n = 0, 4) 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register.
PAGE 122
High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Figure 57.
PAGE 123
A/T89C51CC01 Figure 58. PCA PWM Mode CCAPnH CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL “0” CL < CCAPnL 8-Bit Comparator CL (8 bits) CEX CL > = CCAPnL “1” PCA Watchdog Timer ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board Watchdog timer is available with the PCA to improve system reliability without increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge.
PAGE 124
PCA Registers Table 100. CMOD Register CMOD (S:D9h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 7 CIDL 6 WDTE 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 125
A/T89C51CC01 Table 101. CCON Register CCON (S:D8h) PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
PAGE 126
Table 102. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number 7:0 Bit Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 103.
PAGE 127
A/T89C51CC01 Table 104. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number 7 Bit Mnemonic Description - Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function.
PAGE 128
Table 105. CH Register CH (S:F9h) PCA Counter Register High Value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7:0 Bit Mnemonic Description CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 106.
PAGE 129
A/T89C51CC01 Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the T89C51CC01. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two modes of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits).
PAGE 130
Figure 59. ADC Description ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 IEN1.1 ADCIN Rai SAR Cai AVSS ADDH 2 ADDL - Sample and Hold 111 8 + 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 60 shows the timing diagram of a complete conversion.
PAGE 131
A/T89C51CC01 ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for rearming the interrupt.
PAGE 132
Figure 61. A/D Converter clock CPU CLOCK ADC Clock Prescaler ADCLK ÷2 A/D CPU Core Clock Symbol Converter ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is reduced. IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 62.
PAGE 133
A/T89C51CC01 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt: EA = 1 133 4129N–CAN–03/08
PAGE 134
Registers Table 108. ADCF Register ADCF (S:F6h) ADC Configuration 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7-0 Bit Mnemonic Description CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value = 0000 0000b Table 109.
PAGE 135
A/T89C51CC01 Table 110. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic Description 7-5 - 4-0 PRS4:0 Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler fADC = fcpu clock/ (4 (or 2 in X2 mode)* PRS ) Reset Value = XXX0 0000b Table 111.
PAGE 136
Interrupt System Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 63. Interrupt Control System INT0# 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1# External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.
PAGE 137
A/T89C51CC01 Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination.
PAGE 138
Registers Table 115. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
PAGE 139
A/T89C51CC01 Table 116. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - - ETIM EADC ECAN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 140
Table 117. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPC PCA Interrupt Priority bit Refer to PPCH for priority level 5 PT2 Timer 2 Overflow Interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial Port Priority bit Refer to PSH for priority level.
PAGE 141
A/T89C51CC01 Table 118. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 - - - - Bit Number 3 2 1 0 POVRL PADCL PCANL Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
PAGE 142
Table 119. IPH0 Register IPH0 (B7h) Interrupt High Priority Register 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit.
PAGE 143
A/T89C51CC01 Table 120. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1 7 6 5 4 - - - - Bit Number 3 2 1 0 POVRH PADCH PCANH Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
PAGE 144
Electrical Characteristics Absolute Maximum Ratings *NOTICE: Ambiant Temperature Under Bias: I = industrial ....................................................... -40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC from VSS ......................................-0.5V to + 6V Voltage on Any Pin from VSS .................... -0.5V to VCC + 0.2 V Power Dissipation ..............................................................
PAGE 145
A/T89C51CC01 Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 67.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 64.). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 65.). 3.
PAGE 146
Figure 65. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 66. ICC Test Condition, Power-Down Mode VCC ICC VCC VCC P0 RST (NC) EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 67. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 146 0.7VCC 0.2VCC-0.
PAGE 147
A/T89C51CC01 DC Parameters for A/D Converter Table 122. DC Parameters for AD Converter in Precision Conversion Symbol AVin Rref (2) Varef Parameter Min Analog input voltage Vss- 0.2 Resistance between Vref and Vss Reference voltage Cai Analog input Capacitance Rai Analog input Resistor INL Integral non linearity DNL Differential non linearity OE Offset error Typ(1) 12 Max Unit Vref + 0.2 V 24 kΩ 3.00 V 16 2.40 60 pF During sampling 400 Ω During sampling 1 2 lsb 0.
PAGE 148
External Program Memory Characteristics Table 123. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 124.
PAGE 149
A/T89C51CC01 Table 125. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TLHLL Min 2T-x T-x 10 ns TAVLL Min T-x 0.5 T - x 15 ns TLLAX Min T-x 0.5 T - x 15 ns TLLIV Max 4T-x 2T-x 30 ns TLLPL Min T-x 0.5 T - x 10 ns TPLPH Min 3T-x 1.5 T - x 20 ns TPLIV Max 3T-x 1.5 T - x 40 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 7 ns TAVIV Max 5T-x 2.
PAGE 150
External Data Memory Characteristics Table 126. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Table 127.
PAGE 151
A/T89C51CC01 Table 128. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TRLRH Min 6T-x 3T-x 20 ns TWLWH Min 6T-x 3T-x 20 ns TRLDV Max 5T-x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 ns TLLDV Max 8T-x 4T -x 40 ns TAVDV Max 9T-x 4.5 T - x 60 ns TLLWL Min 3T-x 1.5 T - x 25 ns TLLWL Max 3T+x 1.5 T + x 25 ns TAVWL Min 4T-x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.
PAGE 152
External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TQVWX TLLAX PORT 0 A0-A7 TWHQX TQVWH DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL RD TRLRH TRHDZ TAVDV TLLAX PORT 0 TAVWL PORT 2 TRHDX A0-A7 ADDRESS OR SFR-P2 DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 Serial Port Timing – Shift Register Mode Table 129.
PAGE 153
A/T89C51CC01 Table 130. AC Parameters for a Fix Clock (F = 40 MHz) Symbol Min Max TXLXL 300 ns TQVHX 200 ns TXHQX 30 ns TXHDX 0 ns TXHDV Units 117 ns Table 131.
PAGE 154
External Clock Drive Waveforms VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCX TCLCH TCLCX TCHCL TCLCL AC Testing Input/Output Waveforms VCC -0.5V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.
PAGE 155
A/T89C51CC01 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
PAGE 156
Flash/EEPROM Memory Table 133. Timing Symbol Definitions Signals Conditions S (Hardware condition) PSEN#,EA L Low R RST V Valid B FBUSY flag X No Longer Valid Table 134. Memory AC Timing VDD = 3V to 5.5V, TA = -40 to +85°C Symbol Parameter TSVRL Input PSEN# Valid to RST Edge 50 ns TRLSX Input PSEN# Hold after RST Edge 50 ns TBHBL Min Typ Max Unit Flash/EEPROM Internal Busy (Programming) Time (2.7 V) 14 21 ms Flash/EEPROM Internal Busy (Programming) Time (3.
PAGE 157
A/T89C51CC01 Ordering Information Table 136.
PAGE 158
Package Drawings VQFP44 158 A/T89C51CC01 4129N–CAN–03/08
PAGE 159
A/T89C51CC01 STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
PAGE 160
PLCC44 160 A/T89C51CC01 4129N–CAN–03/08
PAGE 161
A/T89C51CC01 STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
PAGE 162
Datasheet Change Log for T89C51CC01 Changes from 4129F 11/02 to 4129G - 04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles. Changes from 4129G 04/03 to 4129H - 10/03 1. Updated “Electrical Characteristics” on page 144. Changes from 4129H 10/03 to 4129I - 12/03 1. Correction in Registers CPA and CPS0. Changes from 4129I 12/03 to 4129J - 08/04 1. Figure clock-out mode modified see, Figure 37 on page 67. 2.
PAGE 163
Table of Contents Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configuration .................................................................................. 3 I/O Configurations .................................
PAGE 164
Program/Code Memory ...................................................................... 33 External Code Memory Access ........................................................................... 34 Flash Memory Architecture ................................................................................ 35 Overview of FM0 Operations.............................................................................. 37 Registers ...................................................................................
PAGE 165
Table of Contents CAN Controller Description ................................................................................ 79 CAN Controller Mailbox and Registers Organization ......................................... 80 CAN Controller Management ............................................................................. 82 IT CAN Management........................................................................................... 84 Bit Timing and Baud Rate ...........................................
PAGE 166
Absolute Maximum Ratings ............................................................................. DC Parameters for Standard Voltage............................................................... DC Parameters for A/D Converter.................................................................... AC Parameters ................................................................................................. 144 144 147 147 Ordering Information ............................................................
PAGE 167
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.