Datasheet

AT89C51AC3

4383D–8051–02/08

Figure 52. SPI Interrupt Requests Generation

Registers Three registers in the SPI module provide control, status and data storage functions.

These registers are describe in the following paragraphs.

Serial Peripheral Control

• The Serial Peripheral Control Register does the following:

• Selects one of the Master clock rates

• Configure the SPI Module as Master or Slave

• Selects serial clock polarity and phase

• Enables the SPI Module

• Frees the SS pin for a general-purpose

Table 48 describes this register and explains the use of each bit

Table 48. SPCON Register

SPCON - Serial Peripheral Control Register (0D4H)

SPI

CPU Interrupt Request

SPIF

SPTEIE

SPTE

MODF

MODFIE

7 6 5 4 3 2 1 0

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

Bit Number Bit Mnemonic Description

7 SPR2

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and

SPR0 for detail).

6 SPEN

Serial Peripheral Enable

Cleared to disable the SPI interface (internal reset of the SPI).

Set to enable the SPI interface.

5 SSDIS

SS Disable

Cleared to enable SS in both Master and Slave modes.

Set to disable SS in both Master and Slave modes. In Slave mode,

this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF

interrupt request is generated

4 MSTR

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.